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authorKorey Sewell <ksewell@umich.edu>2011-02-23 01:01:46 -0500
committerKorey Sewell <ksewell@umich.edu>2011-02-23 01:01:46 -0500
commitfb9257841559f589cd9369a210715106239917fe (patch)
treecca07d9a6b90dafb3db5ed61f0a2c1568912710b /configs/common/CacheConfig.py
parent78c37b804833da8777ce9a72247577dd719b5439 (diff)
downloadgem5-fb9257841559f589cd9369a210715106239917fe.tar.xz
configs: set default cache params
It's confusing (especially to new users), when you are setting some standard parameters (as defined in Options.py) and they aren't reflected in the simulations so we might as well link the settings in CacheConfig.py to those in Options.py
Diffstat (limited to 'configs/common/CacheConfig.py')
-rw-r--r--configs/common/CacheConfig.py10
1 files changed, 5 insertions, 5 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 461551817..233f504bc 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -35,7 +35,7 @@ from Caches import *
def config_cache(options, system):
if options.l2cache:
- system.l2 = L2Cache(size='2MB')
+ system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc)
system.tol2bus = Bus()
system.l2.cpu_side = system.tol2bus.port
system.l2.mem_side = system.membus.port
@@ -43,14 +43,14 @@ def config_cache(options, system):
for i in xrange(options.num_cpus):
if options.caches:
+ icache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc)
+ dcache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc)
if buildEnv['TARGET_ISA'] == 'x86':
- system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
- L1Cache(size = '64kB'),
+ system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
PageTableWalkerCache(),
PageTableWalkerCache())
else:
- system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
- L1Cache(size = '64kB'))
+ system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
if options.l2cache:
system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
else: