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| author | Andreas Sandberg <andreas@sandberg.pp.se> | 2013-09-30 12:20:53 +0200 |
|---|---|---|
| committer | Andreas Sandberg <andreas@sandberg.pp.se> | 2013-09-30 12:20:53 +0200 |
| commit | fec2dea5c35d830ab4f4dc5295e6dba0e152f18e (patch) | |
| tree | d3304bcc3a5d3d7684df0107982077714200535f /configs/common/CacheConfig.py | |
| parent | d9856f33a455b9c86b90f5857df866fba3aa5bfb (diff) | |
| download | gem5-fec2dea5c35d830ab4f4dc5295e6dba0e152f18e.tar.xz | |
x86: Add support for m5ops through a memory mapped interface
In order to support m5ops in virtualized environments, we need to use
a memory mapped interface. This changeset adds support for that by
reserving 0xFFFF0000-0xFFFFFFFF and mapping those to the generic IPR
interface for m5ops. The mapping is done in the
X86ISA::TLB::finalizePhysical() which means that it just works for all
of the CPU models, including virtualized ones.
Diffstat (limited to 'configs/common/CacheConfig.py')
0 files changed, 0 insertions, 0 deletions