summaryrefslogtreecommitdiff
path: root/configs/common/CacheConfig.py
diff options
context:
space:
mode:
authorAbdul Mutaal Ahmad <abdul.mutaal@gmail.com>2016-07-01 09:45:21 -0500
committerAbdul Mutaal Ahmad <abdul.mutaal@gmail.com>2016-07-01 09:45:21 -0500
commit7cb0c7bd65a61f7f0bf75a1f0b2eaffb185bf112 (patch)
tree79e135da2206b0785f4becae2c82dab1aa6ecdbc /configs/common/CacheConfig.py
parent1051223318360a74c46c0f818bdc599287a51064 (diff)
downloadgem5-7cb0c7bd65a61f7f0bf75a1f0b2eaffb185bf112.tar.xz
mem: different HMC configuration
In this new hmc configuration we have used the existing components in gem5 mainly [SerialLink] [NoncoherentXbar]& [DRAMCtrl] to define 3 different architecture for HMC. Highlights 1- It explores 3 different HMC architectures 2- It creates 4-HMC crossbars and attaches 16 vault controllers with it. This will connect vaults to serial links 3- From the previous version, HMCController with round robin funtionality is being removed and all the serial links are being accessible directly from user ports 4- Latency incorporated by HMCController (in previous version) is being added to SerialLink Committed by Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'configs/common/CacheConfig.py')
0 files changed, 0 insertions, 0 deletions