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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:14:39 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:14:39 -0400 |
| commit | 893533a1264bb369b47f74493adf30ce22829f34 (patch) | |
| tree | 07c750519f5ac1b972be47a0ca6f68ee517d9f07 /configs/common/CacheConfig.py | |
| parent | a262908acc0a641700a03fcea89c48133f0467cd (diff) | |
| download | gem5-893533a1264bb369b47f74493adf30ce22829f34.tar.xz | |
mem: Allow read-only caches and check compliance
This patch adds a parameter to the BaseCache to enable a read-only
cache, for example for the instruction cache, or table-walker cache
(not for x86). A number of checks are put in place in the code to
ensure a read-only cache does not end up with dirty data.
A follow-on patch adds suitable read requests to allow a read-only
cache to explicitly ask for clean data.
Diffstat (limited to 'configs/common/CacheConfig.py')
| -rw-r--r-- | configs/common/CacheConfig.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index 899090af5..d54df7490 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -64,7 +64,7 @@ def config_cache(options, system): O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2 else: dcache_class, icache_class, l2_cache_class = \ - L1Cache, L1Cache, L2Cache + L1_DCache, L1_ICache, L2Cache # Set the cache line size of the system system.cache_line_size = options.cacheline_size |