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| author | Radhika Jagtap <radhika.jagtap@ARM.com> | 2015-12-07 16:42:16 -0600 |
|---|---|---|
| committer | Radhika Jagtap <radhika.jagtap@ARM.com> | 2015-12-07 16:42:16 -0600 |
| commit | 9bd5051b6022249f95364ef30b100b69ac7e7c37 (patch) | |
| tree | 81ee5797338a1ed3660093dc600156e286c82a01 /configs/common/CacheConfig.py | |
| parent | 8f1ca0a212ede0ecac1199027681f3c2ca9308db (diff) | |
| download | gem5-9bd5051b6022249f95364ef30b100b69ac7e7c37.tar.xz | |
config: Enable elastic trace capture and replay in se/fs
This patch adds changes to the configuration scripts to support elastic
tracing and replay.
The patch adds a command line option to enable elastic tracing in SE mode
and FS mode. When enabled the Elastic Trace cpu probe is attached to O3CPU
and a few O3 CPU parameters are tuned. The Elastic Trace probe writes out
both instruction fetch and data dependency traces. The patch also enables
configuring the TraceCPU to replay traces using the SE and FS script.
The replay run is designed to resume from checkpoint using atomic cpu to
restore state keeping it consistent with FS run flow. It then switches to
TraceCPU to replay the input traces.
Diffstat (limited to 'configs/common/CacheConfig.py')
| -rw-r--r-- | configs/common/CacheConfig.py | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index d54df7490..b96a7011c 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -69,6 +69,13 @@ def config_cache(options, system): # Set the cache line size of the system system.cache_line_size = options.cacheline_size + # If elastic trace generation is enabled, make sure the memory system is + # minimal so that compute delays do not include memory access latencies. + # Configure the compulsory L1 caches for the O3CPU, do not configure + # any more caches. + if options.l2cache and options.elastic_trace_en: + fatal("When elastic trace is enabled, do not configure L2 caches.") + if options.l2cache: # Provide a clock for the L2 and the L1-to-L2 bus here as they # are not connected using addTwoLevelCacheHierarchy. Use the |