config: Update script to set cache line size on system

This patch changes the config scripts such that they do not set the
cache line size per cache instance, but rather for the system as a
whole.

1 files changed, 6 insertions, 6 deletions

diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 4b4ce7553..b467b1656 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -59,6 +59,9 @@ def config_cache(options, system):
         dcache_class, icache_class, l2_cache_class = \
             L1Cache, L1Cache, L2Cache
 
+    # Set the cache line size of the system
+    system.cache_line_size = options.cacheline_size
+
     if options.l2cache:
         # Provide a clock for the L2 and the L1-to-L2 bus here as they
         # are not connected using addTwoLevelCacheHierarchy. Use the
@@ -66,8 +69,7 @@ def config_cache(options, system):
         # bytes (256 bits).
         system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
                                    size=options.l2_size,
-                                   assoc=options.l2_assoc,
-                                   block_size=options.cacheline_size)
+                                   assoc=options.l2_assoc)
 
         system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain,
                                      width = 32)
@@ -77,11 +79,9 @@ def config_cache(options, system):
     for i in xrange(options.num_cpus):
         if options.caches:
             icache = icache_class(size=options.l1i_size,
-                                  assoc=options.l1i_assoc,
-                                  block_size=options.cacheline_size)
+                                  assoc=options.l1i_assoc)
             dcache = dcache_class(size=options.l1d_size,
-                                  assoc=options.l1d_assoc,
-                                  block_size=options.cacheline_size)
+                                  assoc=options.l1d_assoc)
 
             # When connecting the caches, the clock is also inherited
             # from the CPU in question