mem: Allow read-only caches and check compliance

This patch adds a parameter to the BaseCache to enable a read-only
cache, for example for the instruction cache, or table-walker cache
(not for x86). A number of checks are put in place in the code to
ensure a read-only cache does not end up with dirty data.

A follow-on patch adds suitable read requests to allow a read-only
cache to explicitly ask for clean data.

1 files changed, 11 insertions, 0 deletions

diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 6687a967c..2bdffc6c7 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -54,6 +54,12 @@ class L1Cache(BaseCache):
     tgts_per_mshr = 20
     is_top_level = True
 
+class L1_ICache(L1Cache):
+    is_read_only = True
+
+class L1_DCache(L1Cache):
+    pass
+
 class L2Cache(BaseCache):
     assoc = 8
     hit_latency = 20
@@ -81,3 +87,8 @@ class PageTableWalkerCache(BaseCache):
     tgts_per_mshr = 12
     forward_snoops = False
     is_top_level = True
+    # the x86 table walker actually writes to the table-walker cache
+    if buildEnv['TARGET_ISA'] == 'x86':
+        is_read_only = False
+    else:
+        is_read_only = True