X86: Add L1 caches for the TLB walkers.

Small L1 caches are connected to the TLB walkers when caches are used. This
allows them to participate in the coherence protocol properly.

1 files changed, 8 insertions, 0 deletions

diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 412cfd3b1..3adc7e5c9 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -42,6 +42,14 @@ class L2Cache(BaseCache):
     mshrs = 20
     tgts_per_mshr = 12
 
+class PageTableWalkerCache(BaseCache):
+    assoc = 2
+    block_size = 64
+    latency = '1ns'
+    mshrs = 10
+    size = '1kB'
+    tgts_per_mshr = 12
+
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64