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authorAndreas Hansson <andreas.hansson@arm.com>2015-08-21 07:03:23 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-08-21 07:03:23 -0400
commitddfa96cf455ba4a287930942514cdf0f7f2afa77 (patch)
tree89eddf6ab0ec6f4660629b45b1b7cff7df6ca82c /configs/common/Caches.py
parentd71a0d790d8d1113480c5a57d7bfbb9b7d0d0037 (diff)
downloadgem5-ddfa96cf455ba4a287930942514cdf0f7f2afa77.tar.xz
mem: Add explicit Cache subclass and make BaseCache abstract
Open up for other subclasses to BaseCache and transition to using the explicit Cache subclass. --HG-- rename : src/mem/cache/BaseCache.py => src/mem/cache/Cache.py
Diffstat (limited to 'configs/common/Caches.py')
-rw-r--r--configs/common/Caches.py8
1 files changed, 4 insertions, 4 deletions
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index cfb873b5e..0a3c56297 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -46,7 +46,7 @@ from m5.objects import *
# starting point, and specific parameters can be overridden in the
# specific instantiations.
-class L1Cache(BaseCache):
+class L1Cache(Cache):
assoc = 2
hit_latency = 2
response_latency = 2
@@ -59,7 +59,7 @@ class L1_ICache(L1Cache):
class L1_DCache(L1Cache):
pass
-class L2Cache(BaseCache):
+class L2Cache(Cache):
assoc = 8
hit_latency = 20
response_latency = 20
@@ -67,7 +67,7 @@ class L2Cache(BaseCache):
tgts_per_mshr = 12
write_buffers = 8
-class IOCache(BaseCache):
+class IOCache(Cache):
assoc = 8
hit_latency = 50
response_latency = 50
@@ -76,7 +76,7 @@ class IOCache(BaseCache):
tgts_per_mshr = 12
forward_snoops = False
-class PageTableWalkerCache(BaseCache):
+class PageTableWalkerCache(Cache):
assoc = 2
hit_latency = 2
response_latency = 2