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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:20:19 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:20:19 -0500 |
| commit | a432d8e0851de8d090676697e29ca6ed4be64fb7 (patch) | |
| tree | 50546c6a98e9d766ad53aa05eb75381ce6d7f298 /configs/common/Caches.py | |
| parent | 2f40b3b8ae4fddcdd167fc86469254f40736c888 (diff) | |
| download | gem5-a432d8e0851de8d090676697e29ca6ed4be64fb7.tar.xz | |
Mem: Fix issue with dirty block being lost when entire block transferred to non-cache.
This change fixes the problem for all the cases we actively use. If you want to try
more creative I/O device attachments (E.g. sharing an L2), this won't work. You
would need another level of caching between the I/O device and the cache
(which you actually need anyway with our current code to make sure writes
propagate). This is required so that you can mark the cache in between as
top level and it won't try to send ownership of a block to the I/O device.
Asserts have been added that should catch any issues.
Diffstat (limited to 'configs/common/Caches.py')
| -rw-r--r-- | configs/common/Caches.py | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/configs/common/Caches.py b/configs/common/Caches.py index 3adc7e5c9..ffcd63c49 100644 --- a/configs/common/Caches.py +++ b/configs/common/Caches.py @@ -34,6 +34,7 @@ class L1Cache(BaseCache): latency = '1ns' mshrs = 10 tgts_per_mshr = 5 + is_top_level = True class L2Cache(BaseCache): assoc = 8 @@ -49,6 +50,7 @@ class PageTableWalkerCache(BaseCache): mshrs = 10 size = '1kB' tgts_per_mshr = 12 + is_top_level = True class IOCache(BaseCache): assoc = 8 @@ -58,3 +60,4 @@ class IOCache(BaseCache): size = '1kB' tgts_per_mshr = 12 forward_snoops = False + is_top_level = True |