diff options
| author | Steve Reinhardt <Steve.Reinhardt@amd.com> | 2008-07-16 11:10:33 -0700 |
|---|---|---|
| committer | Steve Reinhardt <Steve.Reinhardt@amd.com> | 2008-07-16 11:10:33 -0700 |
| commit | 6629d9b2bc58a885bfebce1517fd12483497b6e4 (patch) | |
| tree | 22e2bc30405ba483ac571951f49cc77d7e713477 /configs/common/Caches.py | |
| parent | 05d8c9acb8a5a985956998fc13551288496e5cdc (diff) | |
| download | gem5-6629d9b2bc58a885bfebce1517fd12483497b6e4.tar.xz | |
mem: use single BadAddr responder per system.
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond. Now there is just one on
the main memory bus. The default bus responder on all other buses
is now the downstream cache's cpu_side port. Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.
Diffstat (limited to 'configs/common/Caches.py')
| -rw-r--r-- | configs/common/Caches.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/configs/common/Caches.py b/configs/common/Caches.py index f1ea957b5..1c3b089c7 100644 --- a/configs/common/Caches.py +++ b/configs/common/Caches.py @@ -50,3 +50,4 @@ class IOCache(BaseCache): mshrs = 20 size = '1kB' tgts_per_mshr = 12 + forward_snoops = False |