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authorMrinmoy Ghosh <mrinmoy.ghosh@arm.com>2012-09-25 11:49:41 -0500
committerMrinmoy Ghosh <mrinmoy.ghosh@arm.com>2012-09-25 11:49:41 -0500
commit6fc0094337bc0356c55232c3850fb5fd2dab1f0c (patch)
treef23261eb3f3a7e91b08505e68015941b1d04ba7c /configs/common/Caches.py
parent74ab69c7eafc2f0d187ce3ba7d6b9a59ba291b9f (diff)
downloadgem5-6fc0094337bc0356c55232c3850fb5fd2dab1f0c.tar.xz
Cache: add a response latency to the caches
In the current caches the hit latency is paid twice on a miss. This patch lets a configurable response latency be set of the cache for the backward path.
Diffstat (limited to 'configs/common/Caches.py')
-rw-r--r--configs/common/Caches.py12
1 files changed, 8 insertions, 4 deletions
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 0be8001d7..f16a83559 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -31,7 +31,8 @@ from m5.objects import *
class L1Cache(BaseCache):
assoc = 2
block_size = 64
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
mshrs = 10
tgts_per_mshr = 20
is_top_level = True
@@ -39,14 +40,16 @@ class L1Cache(BaseCache):
class L2Cache(BaseCache):
assoc = 8
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 20
tgts_per_mshr = 12
class PageTableWalkerCache(BaseCache):
assoc = 2
block_size = 64
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
mshrs = 10
size = '1kB'
tgts_per_mshr = 12
@@ -55,7 +58,8 @@ class PageTableWalkerCache(BaseCache):
class IOCache(BaseCache):
assoc = 8
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12