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authorAndreas Hansson <andreas.hansson@arm.com>2016-02-10 04:08:24 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2016-02-10 04:08:24 -0500
commitfbdeb6031664d71e19a25f51b6ee882d803dac30 (patch)
tree0a3fa9a980e9b9a1013b3aff37080b045192b650 /configs/common/Caches.py
parentbead7f249a71f8b15ae92b0df9822abb52ca7323 (diff)
downloadgem5-fbdeb6031664d71e19a25f51b6ee882d803dac30.tar.xz
mem: Deduce if cache should forward snoops
This patch changes how the cache determines if snoops should be forwarded from the memory side to the CPU side. Instead of having a parameter, the cache now looks at the port connected on the CPU side, and if it is a snooping port, then snoops are forwarded. Less error prone, and less parameters to worry about. The patch also tidies up the CPU classes to ensure that their I-side port is not snooping by removing overrides to the snoop request handler, such that snoop requests will panic via the default MasterPort implement
Diffstat (limited to 'configs/common/Caches.py')
-rw-r--r--configs/common/Caches.py3
1 files changed, 1 insertions, 2 deletions
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index c65910e23..af1dee626 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -76,7 +76,6 @@ class IOCache(Cache):
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
- forward_snoops = False
class PageTableWalkerCache(Cache):
assoc = 2
@@ -85,7 +84,7 @@ class PageTableWalkerCache(Cache):
mshrs = 10
size = '1kB'
tgts_per_mshr = 12
- forward_snoops = False
+
# the x86 table walker actually writes to the table-walker cache
if buildEnv['TARGET_ISA'] == 'x86':
is_read_only = False