summaryrefslogtreecommitdiff
path: root/configs/common/CpuConfig.py
diff options
context:
space:
mode:
authorPierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>2017-03-22 18:36:13 +0100
committerPierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>2017-05-18 14:56:08 +0000
commit5bf2a86c6a8a1fc68422053e1a782d3efe0e6f3c (patch)
tree141c914c052d2f9eaedc52430b0960197d471263 /configs/common/CpuConfig.py
parentaa651c7f8321bf96fc88f9a17285225000a753ec (diff)
downloadgem5-5bf2a86c6a8a1fc68422053e1a782d3efe0e6f3c.tar.xz
arm, config: added support for ex5 model of big.LITTLE
This patch enables using calibrated big and LITTLE cores, ex5_big and ex5_LITTLE instead of the default 'arm_detailed' and 'minor' cpus. The ex5 model is based on the Samsung Exynos 5 Octa (5422) SoC. Operation and memory hierarchy latencies have been calibrated using the lmbench micro-benchmark suite. The preliminary validation results have been published as: 'Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration', in International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC'16), Lyon, France (Sep, 2016). From http://reviews.gem5.org/r/3666 Change-Id: I4935dee0a9222bd1bf7adfccb9443014945bb2d7 Signed-off-by: Anastasiia Butko <abutko@lbl.gov> Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> Reviewed-on: https://gem5-review.googlesource.com/2464 Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'configs/common/CpuConfig.py')
-rw-r--r--configs/common/CpuConfig.py14
1 files changed, 14 insertions, 0 deletions
diff --git a/configs/common/CpuConfig.py b/configs/common/CpuConfig.py
index 8810622aa..28267c7dd 100644
--- a/configs/common/CpuConfig.py
+++ b/configs/common/CpuConfig.py
@@ -117,6 +117,20 @@ try:
except:
pass
+# The calibrated ex5-model cores
+try:
+ from ex5_LITTLE import ex5_LITTLE
+ _cpu_classes["ex5_LITTLE"] = ex5_LITTLE
+except:
+ pass
+
+try:
+ from ex5_big import ex5_big
+ _cpu_classes["ex5_big"] = ex5_big
+except:
+ pass
+
+
# Add all CPUs in the object hierarchy.
for name, cls in inspect.getmembers(m5.objects, is_cpu_class):
_cpu_classes[name] = cls