config: Add a mem-type config option to se/fs scripts

This patch enables selection of the memory controller class through a
mem-type command-line option. Behind the scenes, this option is
treated much like the cpu-type, and a similar framework is used to
resolve the valid options, and translate the short-hand description to
a valid class.

The regression scripts are updated with a hardcoded memory class for
the moment. The best solution going forward is probably to get the
memory out of the makeSystem functions, but Ruby complicates things as
it does not connect the memory controller to the membus.

--HG--
rename : configs/common/CpuConfig.py => configs/common/MemConfig.py

1 files changed, 24 insertions, 23 deletions

diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 3a7a50839..0d46dcde2 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -55,7 +55,7 @@ class MemBus(CoherentBus):
     default = Self.badaddr_responder.pio
 
 
-def makeLinuxAlphaSystem(mem_mode, mdesc = None):
+def makeLinuxAlphaSystem(mem_mode, MemClass, mdesc = None):
     IO_address_space_base = 0x80000000000
     class BaseTsunami(Tsunami):
         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
@@ -73,7 +73,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
     # base address (including the PCI config space)
     self.bridge = Bridge(delay='50ns',
                          ranges = [AddrRange(IO_address_space_base, Addr.max)])
-    self.physmem = SimpleDDR3(range = AddrRange(mdesc.mem()))
+    self.physmem = MemClass(range = AddrRange(mdesc.mem()))
     self.mem_ranges = [self.physmem.range]
     self.bridge.master = self.iobus.slave
     self.bridge.slave = self.membus.master
@@ -104,13 +104,13 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
 
     return self
 
-def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
+def makeLinuxAlphaRubySystem(mem_mode, MemClass, mdesc = None):
     class BaseTsunami(Tsunami):
         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
                             pci_func=0, pci_dev=0, pci_bus=0)
         
-    physmem = SimpleDDR3(range = AddrRange(mdesc.mem()))
+    physmem = MemClass(range = AddrRange(mdesc.mem()))
     self = LinuxAlphaSystem(physmem = physmem)
     self.mem_ranges = [self.physmem.range]
     if not mdesc:
@@ -157,7 +157,7 @@ def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
 
     return self
 
-def makeSparcSystem(mem_mode, mdesc = None):
+def makeSparcSystem(mem_mode, MemClass, mdesc = None):
     # Constants from iob.cc and uart8250.cc
     iob_man_addr = 0x9800000000
     uart_pio_size = 8
@@ -180,10 +180,10 @@ def makeSparcSystem(mem_mode, mdesc = None):
     self.t1000 = T1000()
     self.t1000.attachOnChipIO(self.membus)
     self.t1000.attachIO(self.iobus)
-    self.physmem = SimpleDDR3(range = AddrRange(Addr('1MB'), size = '64MB'),
-                              zero = True)
-    self.physmem2 = SimpleDDR3(range = AddrRange(Addr('2GB'), size ='256MB'),
-                               zero = True)
+    self.physmem = MemClass(range = AddrRange(Addr('1MB'), size = '64MB'),
+                            zero = True)
+    self.physmem2 = MemClass(range = AddrRange(Addr('2GB'), size ='256MB'),
+                             zero = True)
     self.mem_ranges = [self.physmem.range, self.physmem2.range]
     self.bridge.master = self.iobus.slave
     self.bridge.slave = self.membus.master
@@ -227,8 +227,8 @@ def makeSparcSystem(mem_mode, mdesc = None):
 
     return self
 
-def makeArmSystem(mem_mode, machine_type, mdesc = None, dtb_filename = None,
-                  bare_metal=False):
+def makeArmSystem(mem_mode, machine_type, MemClass, mdesc = None,
+                  dtb_filename = None, bare_metal=False):
     assert machine_type
 
     if bare_metal:
@@ -275,8 +275,8 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, dtb_filename = None,
     if bare_metal:
         # EOT character on UART will end the simulation
         self.realview.uart.end_on_eot = True
-        self.physmem = SimpleDDR3(range = AddrRange(Addr(mdesc.mem())),
-                                  zero = True)
+        self.physmem = MemClass(range = AddrRange(Addr(mdesc.mem())),
+                                zero = True)
         self.mem_ranges = [self.physmem.range]
     else:
         self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
@@ -292,10 +292,9 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, dtb_filename = None,
         boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
                      'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
 
-        self.physmem = SimpleDDR3(range =
-                                  AddrRange(self.realview.mem_start_addr,
-                                            size = mdesc.mem()),
-                                  conf_table_reported = True)
+        self.physmem = MemClass(range = AddrRange(self.realview.mem_start_addr,
+                                                  size = mdesc.mem()),
+                                conf_table_reported = True)
         self.mem_ranges = [self.physmem.range]
         self.realview.setupBootLoader(self.membus, self, binary)
         self.gic_cpu_addr = self.realview.gic.cpu_addr
@@ -317,7 +316,7 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, dtb_filename = None,
     return self
 
 
-def makeLinuxMipsSystem(mem_mode, mdesc = None):
+def makeLinuxMipsSystem(mem_mode, MemClass, mdesc = None):
     class BaseMalta(Malta):
         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
@@ -331,7 +330,7 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None):
     self.iobus = NoncoherentBus()
     self.membus = MemBus()
     self.bridge = Bridge(delay='50ns')
-    self.physmem = SimpleDDR3(range = AddrRange('1GB'))
+    self.physmem = MemClass(range = AddrRange('1GB'))
     self.mem_ranges = [self.physmem.range]
     self.bridge.master = self.iobus.slave
     self.bridge.slave = self.membus.master
@@ -425,7 +424,8 @@ def connectX86RubySystem(x86_sys):
     x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
 
 
-def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False):
+def makeX86System(mem_mode, MemClass, numCPUs = 1, mdesc = None, self = None,
+                  Ruby = False):
     if self == None:
         self = X86System()
 
@@ -437,7 +437,7 @@ def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False
     self.mem_mode = mem_mode
 
     # Physical memory
-    self.physmem = SimpleDDR3(range = AddrRange(mdesc.mem()))
+    self.physmem = MemClass(range = AddrRange(mdesc.mem()))
     self.mem_ranges = [self.physmem.range]
 
     # Platform
@@ -521,11 +521,12 @@ def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False
     self.intel_mp_table.base_entries = base_entries
     self.intel_mp_table.ext_entries = ext_entries
 
-def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
+def makeLinuxX86System(mem_mode, MemClass, numCPUs = 1, mdesc = None,
+                       Ruby = False):
     self = LinuxX86System()
 
     # Build up the x86 system and then specialize it for Linux
-    makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
+    makeX86System(mem_mode, MemClass, numCPUs, mdesc, self, Ruby)
 
     # We assume below that there's at least 1MB of memory. We'll require 2
     # just to avoid corner cases.