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authorGabe Black <gblack@eecs.umich.edu>2007-05-18 13:36:47 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-05-18 13:36:47 -0700
commita13d5af274a1847eaad649af226e643e86a3322d (patch)
tree6b3bdd0b269802b324b4744e6ed8362d1917e1a0 /configs/common/FSConfig.py
parent6a6e62014ec72f9dd29a42c3e92fbc91d6b1f648 (diff)
parenta8278c3bde2ba9abc2820afafa9d0e766e36b2c8 (diff)
downloadgem5-a13d5af274a1847eaad649af226e643e86a3322d.tar.xz
Merge zizzer.eecs.umich.edu:/bk/newmem
into doughnut.mwconnections.com:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : 3f17fc418ee5a30da2b08a515fb394cc8fcdd237
Diffstat (limited to 'configs/common/FSConfig.py')
-rw-r--r--configs/common/FSConfig.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index be3f5ff79..593baf169 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -61,7 +61,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
self.readfile = mdesc.script()
self.iobus = Bus(bus_id=0)
self.membus = Bus(bus_id=1)
- self.bridge = Bridge()
+ self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns')
self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
self.bridge.side_a = self.iobus.port
self.bridge.side_b = self.membus.port
@@ -94,7 +94,7 @@ def makeSparcSystem(mem_mode, mdesc = None):
self.readfile = mdesc.script()
self.iobus = Bus(bus_id=0)
self.membus = Bus(bus_id=1)
- self.bridge = Bridge()
+ self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns')
self.t1000 = T1000()
self.t1000.attachOnChipIO(self.membus)
self.t1000.attachIO(self.iobus)