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authorGabe Black <gblack@eecs.umich.edu>2006-11-16 12:34:10 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-11-16 12:34:10 -0500
commitcd5b33b9ff4016427fa93655f4bbd9030c4f5612 (patch)
treeb449360088378c982f59568c0a2da0c45cb08c59 /configs/common/FSConfig.py
parent079dd454175ab7fdb3cc429f3cf199bd243c3776 (diff)
downloadgem5-cd5b33b9ff4016427fa93655f4bbd9030c4f5612.tar.xz
Fixes for SPARC_FS
configs/common/FSConfig.py: Make a SPARC system create an IO bus. src/python/m5/objects/T1000.py: Create a T1000 platform src/arch/sparc/miscregfile.cc: Initialize the strand status register to the value legion provides. src/cpu/exetrace.cc: Truncate an ExtMachInst to a MachInst before comparing with Legion. --HG-- extra : convert_revision : e4189b572a5297e8362f5bd26d87b74736c8e5f1
Diffstat (limited to 'configs/common/FSConfig.py')
-rw-r--r--configs/common/FSConfig.py6
1 files changed, 6 insertions, 0 deletions
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 546569f30..b97667780 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -84,8 +84,14 @@ def makeSparcSystem(mem_mode, mdesc = None):
# generic system
mdesc = SysConfig()
self.readfile = mdesc.script()
+ self.iobus = Bus(bus_id=0)
self.membus = Bus(bus_id=1)
+ self.bridge = Bridge()
+ self.t1000 = T1000()
+ self.t1000.attachIO(self.iobus)
self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
+ self.bridge.side_a = self.iobus.port
+ self.bridge.side_b = self.membus.port
self.physmem.port = self.membus.port
self.rom.port = self.membus.port
self.intrctrl = IntrControl()