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| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-07 13:05:38 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-07 13:05:38 -0500 |
| commit | e65de3f5ca1d1a91265d09b1950a2d69c620631b (patch) | |
| tree | 032c2483fde6e6c79e79495862f7ee5dd490ffd9 /configs/common/FSConfig.py | |
| parent | 15a979c6be704a4bb083b64148d1a25d7fc4e682 (diff) | |
| download | gem5-e65de3f5ca1d1a91265d09b1950a2d69c620631b.tar.xz | |
config: Do not use hardcoded physmem in fs script
This patch generalises the address range resolution for the I/O cache
and I/O bridge such that they do not assume a single memory. The patch
involves adding a parameter to the system which is then defined based
on the memories that are to be visible from the I/O subsystem, whether
behind a cache or a bridge.
The change is needed to allow interleaved memory controllers in the
system.
Diffstat (limited to 'configs/common/FSConfig.py')
| -rw-r--r-- | configs/common/FSConfig.py | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index bc49be808..eb0730ffa 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -74,6 +74,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None): self.bridge = Bridge(delay='50ns', ranges = [AddrRange(IO_address_space_base, Addr.max)]) self.physmem = SimpleDRAM(range = AddrRange(mdesc.mem())) + self.mem_ranges = [self.physmem.range] self.bridge.master = self.iobus.slave self.bridge.slave = self.membus.master self.physmem.port = self.membus.master @@ -111,6 +112,7 @@ def makeLinuxAlphaRubySystem(mem_mode, mdesc = None): physmem = SimpleDRAM(range = AddrRange(mdesc.mem())) self = LinuxAlphaSystem(physmem = physmem) + self.mem_ranges = [self.physmem.range] if not mdesc: # generic system mdesc = SysConfig() @@ -182,6 +184,7 @@ def makeSparcSystem(mem_mode, mdesc = None): zero = True) self.physmem2 = SimpleDRAM(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) + self.mem_ranges = [self.physmem.range, self.physmem2.range] self.bridge.master = self.iobus.slave self.bridge.slave = self.membus.master self.physmem.port = self.membus.master @@ -273,6 +276,7 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False): self.realview.uart.end_on_eot = True self.physmem = SimpleDRAM(range = AddrRange(Addr(mdesc.mem())), zero = True) + self.mem_ranges = [self.physmem.range] else: self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') self.machine_type = machine_type @@ -289,6 +293,7 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False): AddrRange(self.realview.mem_start_addr, size = mdesc.mem()), conf_table_reported = True) + self.mem_ranges = [self.physmem.range] self.realview.setupBootLoader(self.membus, self, binary) self.gic_cpu_addr = self.realview.gic.cpu_addr self.flags_addr = self.realview.realview_io.pio_addr + 0x30 @@ -324,6 +329,7 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None): self.membus = MemBus() self.bridge = Bridge(delay='50ns') self.physmem = SimpleDRAM(range = AddrRange('1GB')) + self.mem_ranges = [self.physmem.range] self.bridge.master = self.iobus.slave self.bridge.slave = self.membus.master self.physmem.port = self.membus.master @@ -429,6 +435,7 @@ def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False # Physical memory self.physmem = SimpleDRAM(range = AddrRange(mdesc.mem())) + self.mem_ranges = [self.physmem.range] # Platform self.pc = Pc() |