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authorAndreas Hansson <andreas.hansson@arm.com>2014-12-23 09:31:18 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2014-12-23 09:31:18 -0500
commit59460b91f35efe24a99424c0018d2f9c002e50c8 (patch)
tree3371fdc57dd5a032ff4b5fa4b4d51b796b8e71cd /configs/common/MemConfig.py
parent2f7baf9dbe7fd2cd716885adacf508a5b89e9eb8 (diff)
downloadgem5-59460b91f35efe24a99424c0018d2f9c002e50c8.tar.xz
config: Expose the DRAM ranks as a command-line option
This patch gives the user direct influence over the number of DRAM ranks to make it easier to tune the memory density without affecting the bandwidth (previously the only means of scaling the device count was through the number of channels). The patch also adds some basic sanity checks to ensure that the number of ranks is a power of two (since we rely on bit slices in the address decoding).
Diffstat (limited to 'configs/common/MemConfig.py')
-rw-r--r--configs/common/MemConfig.py12
1 files changed, 9 insertions, 3 deletions
diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index 57066426f..4692c2d0e 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -197,9 +197,15 @@ def config_mem(options, system):
# address mapping in the case of a DRAM
for r in system.mem_ranges:
for i in xrange(nbr_mem_ctrls):
- mem_ctrls.append(create_mem_ctrl(cls, r, i, nbr_mem_ctrls,
- intlv_bits,
- system.cache_line_size.value))
+ mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits,
+ system.cache_line_size.value)
+ # Set the number of ranks based on the command-line
+ # options if it was explicitly set
+ if issubclass(cls, m5.objects.DRAMCtrl) and \
+ options.mem_ranks:
+ mem_ctrl.ranks_per_channel = options.mem_ranks
+
+ mem_ctrls.append(mem_ctrl)
system.mem_ctrls = mem_ctrls