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| author | Erfan Azarkhish <erfan.azarkhish@unibo.it> | 2015-11-03 12:17:56 -0600 |
|---|---|---|
| committer | Erfan Azarkhish <erfan.azarkhish@unibo.it> | 2015-11-03 12:17:56 -0600 |
| commit | 100cbc9cf63af46697f129c9c10f0cc80ff7db9d (patch) | |
| tree | f4b38b12cc07635fe679d4adc6071dfa46d5099e /configs/common/MemConfig.py | |
| parent | 2cb491379b17fde81c91d0a4310e6f823d34d36b (diff) | |
| download | gem5-100cbc9cf63af46697f129c9c10f0cc80ff7db9d.tar.xz | |
mem: hmc: top level design
This patch enables modeling a complete Hybrid Memory Cube (HMC) device. It
highly reuses the existing components in gem5's general memory system with some
small modifications. This changeset requires additional patches to model a
complete HMC device.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'configs/common/MemConfig.py')
| -rw-r--r-- | configs/common/MemConfig.py | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py index 0191554a7..286898798 100644 --- a/configs/common/MemConfig.py +++ b/configs/common/MemConfig.py @@ -39,6 +39,7 @@ import m5.objects import inspect import sys +import HMC from textwrap import TextWrapper # Dictionary of mapping names of real memory controller models to @@ -151,6 +152,14 @@ def config_mem(options, system): them. """ + if ( options.mem_type == "HMC_2500_x32"): + HMC.config_hmc(options, system) + subsystem = system.hmc + xbar = system.hmc.xbar + else: + subsystem = system + xbar = system.membus + if options.tlm_memory: system.external_memory = m5.objects.ExternalSlave( port_type="tlm", @@ -161,11 +170,11 @@ def config_mem(options, system): return if options.external_memory_system: - system.external_memory = m5.objects.ExternalSlave( + subsystem.external_memory = m5.objects.ExternalSlave( port_type=options.external_memory_system, - port_data="init_mem0", port=system.membus.master, + port_data="init_mem0", port=xbar.master, addr_ranges=system.mem_ranges) - system.kernel_addr_check = False + subsystem.kernel_addr_check = False return nbr_mem_ctrls = options.mem_channels @@ -199,8 +208,8 @@ def config_mem(options, system): mem_ctrls.append(mem_ctrl) - system.mem_ctrls = mem_ctrls + subsystem.mem_ctrls = mem_ctrls # Connect the controllers to the membus - for i in xrange(len(system.mem_ctrls)): - system.mem_ctrls[i].port = system.membus.master + for i in xrange(len(subsystem.mem_ctrls)): + subsystem.mem_ctrls[i].port = xbar.master |