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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:11:53 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:11:53 -0400 |
| commit | 7e7b67472af43268558d527ef4b2f072b772408b (patch) | |
| tree | 67ab71c6f64693a2cf941255e6fe913145a9b97f /configs/common/MemConfig.py | |
| parent | a3d582f8e64d3ce4b414d615e2ced8d396434ad2 (diff) | |
| download | gem5-7e7b67472af43268558d527ef4b2f072b772408b.tar.xz | |
mem: More descriptive address-mapping scheme names
This patch adds the row bits to the name of the address mapping
schemes to make it more clear that all the current schemes places the
row bits as the most significant bits.
Diffstat (limited to 'configs/common/MemConfig.py')
| -rw-r--r-- | configs/common/MemConfig.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py index b49995369..e5e701716 100644 --- a/configs/common/MemConfig.py +++ b/configs/common/MemConfig.py @@ -168,7 +168,7 @@ def config_mem(options, system): # If the channel bits are appearing after the column # bits, we need to add the appropriate number of bits # for the row buffer size - if ctrl.addr_mapping.value == 'RaBaChCo': + if ctrl.addr_mapping.value == 'RoRaBaChCo': # This computation only really needs to happen # once, but as we rely on having an instance we # end up having to repeat it for each and every |