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author | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:13 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:13 -0400 |
commit | 83d99aebb1dcbe015e752fd74e9cd5c6b5ea0380 (patch) | |
tree | 34e6051c1dbcc2cf7e86eb38d4de24953c71c772 /configs/common/MemConfig.py | |
parent | d82bffd2979ea9dec286dca1b2d10cadc111293a (diff) | |
download | gem5-83d99aebb1dcbe015e752fd74e9cd5c6b5ea0380.tar.xz |
mem: Add bytes per activate DRAM controller stat
This patch adds a histogram to track how many bytes are accessed in an
open row before it is closed. This metric is useful in characterising
a workload and the efficiency of the DRAM scheduler. For example, a
DDR3-1600 device requires 44 cycles (tRC) before it can activate
another row in the same bank. For a x32 interface (8 bytes per cycle)
that means 8 x 44 = 352 bytes must be transferred to hide the
preparation time.
Diffstat (limited to 'configs/common/MemConfig.py')
0 files changed, 0 insertions, 0 deletions