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author | Andreas Sandberg <andreas.sandberg@arm.com> | 2019-01-26 10:57:44 +0000 |
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committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2019-02-26 10:28:00 +0000 |
commit | 32bbddf2362421021b016d995f5e27b2bceea3a2 (patch) | |
tree | 500971374192fb73f41ee41a4e419a61bfca03b9 /configs/common/MemConfig.py | |
parent | c38a6523ab4df2b57337be0b2446bd9d30be94b4 (diff) | |
download | gem5-32bbddf2362421021b016d995f5e27b2bceea3a2.tar.xz |
configs: Fix Python 3 iterator and exec compatibility issues
Python 2.7 used to return lists for operations such as map and range,
this has changed in Python 3. To make the configs Python 3 compliant,
add explicit conversions from iterators to lists where needed, replace
xrange with range, and fix changes to exec syntax.
This change doesn't fix import paths since that might require us to
restructure the configs slightly.
Change-Id: Idcea8482b286779fc98b4e144ca8f54069c08024
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16002
Reviewed-by: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'configs/common/MemConfig.py')
-rw-r--r-- | configs/common/MemConfig.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py index 36035800f..b6e6663f9 100644 --- a/configs/common/MemConfig.py +++ b/configs/common/MemConfig.py @@ -86,7 +86,7 @@ def print_mem_list(): def mem_names(): """Return a list of valid memory names.""" - return _mem_classes.keys() + return list(_mem_classes.keys()) # Add all memory controllers in the object hierarchy. for name, cls in inspect.getmembers(m5.objects, is_mem_class): @@ -215,7 +215,7 @@ def config_mem(options, system): # array of controllers and set their parameters to match their # address mapping in the case of a DRAM for r in system.mem_ranges: - for i in xrange(nbr_mem_ctrls): + for i in range(nbr_mem_ctrls): mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size) # Set the number of ranks based on the command-line @@ -233,7 +233,7 @@ def config_mem(options, system): subsystem.mem_ctrls = mem_ctrls # Connect the controllers to the membus - for i in xrange(len(subsystem.mem_ctrls)): + for i in range(len(subsystem.mem_ctrls)): if opt_mem_type == "HMC_2500_1x32": subsystem.mem_ctrls[i].port = xbar[i/4].master # Set memory device size. There is an independent controller for |