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| author | Abdul Mutaal Ahmad <abdul.mutaal@gmail.com> | 2016-07-01 09:45:21 -0500 |
|---|---|---|
| committer | Abdul Mutaal Ahmad <abdul.mutaal@gmail.com> | 2016-07-01 09:45:21 -0500 |
| commit | 7cb0c7bd65a61f7f0bf75a1f0b2eaffb185bf112 (patch) | |
| tree | 79e135da2206b0785f4becae2c82dab1aa6ecdbc /configs/common/MemConfig.py | |
| parent | 1051223318360a74c46c0f818bdc599287a51064 (diff) | |
| download | gem5-7cb0c7bd65a61f7f0bf75a1f0b2eaffb185bf112.tar.xz | |
mem: different HMC configuration
In this new hmc configuration we have used the existing components in gem5
mainly [SerialLink] [NoncoherentXbar]& [DRAMCtrl] to define 3 different
architecture for HMC.
Highlights
1- It explores 3 different HMC architectures
2- It creates 4-HMC crossbars and attaches 16 vault controllers with it.
This will connect vaults to serial links
3- From the previous version, HMCController with round robin funtionality
is being removed and all the serial links are being accessible directly
from user ports
4- Latency incorporated by HMCController (in previous version) is being
added to SerialLink
Committed by Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'configs/common/MemConfig.py')
| -rw-r--r-- | configs/common/MemConfig.py | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py index 4685cd5d1..71e3bf460 100644 --- a/configs/common/MemConfig.py +++ b/configs/common/MemConfig.py @@ -153,9 +153,10 @@ def config_mem(options, system): """ if ( options.mem_type == "HMC_2500_x32"): - HMC.config_hmc(options, system) - subsystem = system.hmc - xbar = system.hmc.xbar + HMChost = HMC.config_host_hmc(options, system) + HMC.config_hmc(options, system, HMChost.hmc_host) + subsystem = system.hmc_dev + xbar = system.hmc_dev.xbar else: subsystem = system xbar = system.membus @@ -222,4 +223,7 @@ def config_mem(options, system): # Connect the controllers to the membus for i in xrange(len(subsystem.mem_ctrls)): - subsystem.mem_ctrls[i].port = xbar.master + if (options.mem_type == "HMC_2500_x32"): + subsystem.mem_ctrls[i].port = xbar[i/4].master + else: + subsystem.mem_ctrls[i].port = xbar.master |