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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2015-04-08 15:56:06 -0500 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2015-04-08 15:56:06 -0500 |
| commit | c3268f882029c7501867540ccf04db054fdff084 (patch) | |
| tree | 6c31899946f53d46a0b7bbbfe7fd5dc782dfde2c /configs/common/MemConfig.py | |
| parent | f05cb84ed1a61f81c26e4ea22f98454d12f069aa (diff) | |
| download | gem5-c3268f882029c7501867540ccf04db054fdff084.tar.xz | |
config: Support full-system with SST's memory system
This patch adds an example configuration in ext/sst/tests/ that allows
an SST/gem5 instance to simulate a 4-core AArch64 system with SST's
memHierarchy components providing all the caches and memories.
Diffstat (limited to 'configs/common/MemConfig.py')
| -rw-r--r-- | configs/common/MemConfig.py | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py index b0ac44406..5266667ec 100644 --- a/configs/common/MemConfig.py +++ b/configs/common/MemConfig.py @@ -189,6 +189,14 @@ def config_mem(options, system): them. """ + if options.external_memory_system: + system.external_memory = m5.objects.ExternalSlave( + port_type=options.external_memory_system, + port_data="init_mem0", port=system.membus.master, + addr_ranges=system.mem_ranges) + system.kernel_addr_check = False + return + nbr_mem_ctrls = options.mem_channels import math from m5.util import fatal |