summaryrefslogtreecommitdiff
path: root/configs/common/Simulation.py
diff options
context:
space:
mode:
authorKevin Lim <ktlim@umich.edu>2006-10-31 14:58:09 -0500
committerKevin Lim <ktlim@umich.edu>2006-10-31 14:58:09 -0500
commitf763864786d7b95d46fba6f37e1e9ed601b60733 (patch)
tree33b54ba1b12ffe1555d5235be8d8b89203c4b6d3 /configs/common/Simulation.py
parent5825a6c9d82b813d983b688da5f1ce18c90f774f (diff)
downloadgem5-f763864786d7b95d46fba6f37e1e9ed601b60733.tar.xz
Fix up configs.
configs/common/Simulation.py: Remove mem parameter. configs/example/se.py: Remove debug output that got included in my other push. --HG-- extra : convert_revision : 643c34147f6c6cbb98b8e6d6e8206b9859593ab0
Diffstat (limited to 'configs/common/Simulation.py')
-rw-r--r--configs/common/Simulation.py2
1 files changed, 0 insertions, 2 deletions
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index 5e9c1d339..a05e36bd1 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -67,8 +67,6 @@ def run(options, root, testsys):
switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
- switch_cpus[i].mem = testsys.physmem
- switch_cpus1[i].mem = testsys.physmem
switch_cpus[i].connectMemPorts(testsys.membus)
root.switch_cpus = switch_cpus
root.switch_cpus1 = switch_cpus1