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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-12-06 06:05:28 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-12-06 06:05:28 -0500 |
| commit | 2dcf00bc8b6ca0bdfc8ab9a105f7a7780c763bb4 (patch) | |
| tree | c34b7e7417d0c95255def0cea2a48a72229da344 /configs/common/Simulation.py | |
| parent | be29adf51cb115e7e55321bd58b7f6593e6d0080 (diff) | |
| parent | 54a946604b2fa81c0d58fc41bfe1d82840f44793 (diff) | |
| download | gem5-2dcf00bc8b6ca0bdfc8ab9a105f7a7780c763bb4.tar.xz | |
Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/newmem
src/cpu/o3/commit_impl.hh:
Hand Merge
--HG--
extra : convert_revision : 6984db90d5b5ec71c31f1c345f5a77eed540059e
Diffstat (limited to 'configs/common/Simulation.py')
| -rw-r--r-- | configs/common/Simulation.py | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index 374ff3fc2..e037d0343 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -39,6 +39,9 @@ def setCPUClass(options): if options.timing: TmpClass = TimingSimpleCPU elif options.detailed: + if not options.caches: + print "O3 CPU must be used with caches" + sys.exit(1) TmpClass = DerivO3CPU else: TmpClass = AtomicSimpleCPU |