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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-11-14 01:23:59 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-11-14 01:23:59 -0500 |
| commit | 8d234a4bc5adb6dcf26d73596c45a29e616bb4c2 (patch) | |
| tree | a5e4354cbe61d806cd656f314c48efccaf8f32e2 /configs/common/Simulation.py | |
| parent | 14cb2264c80eb961eab1f80738e0144b6179d1a3 (diff) | |
| parent | 69623a892edbaddc8d68a98766ef09b421ac4ce6 (diff) | |
| download | gem5-8d234a4bc5adb6dcf26d73596c45a29e616bb4c2.tar.xz | |
Merge 141.212.106.238:/home/gblack/m5/newmemmemops
into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem
--HG--
extra : convert_revision : 753831a9f6f79d07e6ee122ab894e24161d2e722
Diffstat (limited to 'configs/common/Simulation.py')
| -rw-r--r-- | configs/common/Simulation.py | 16 |
1 files changed, 4 insertions, 12 deletions
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index a67159a50..374ff3fc2 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -85,10 +85,6 @@ def run(options, root, testsys, cpu_class): if not m5.build_env['FULL_SYSTEM']: switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus[i].clock = testsys.cpu[0].clock - if options.caches: - switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), - L1Cache(size = '64kB')) - switch_cpus[i].connectMemPorts(testsys.membus) root.switch_cpus = switch_cpus switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] @@ -108,19 +104,15 @@ def run(options, root, testsys, cpu_class): switch_cpus[i].clock = testsys.cpu[0].clock switch_cpus_1[i].clock = testsys.cpu[0].clock - if options.caches: - switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), - L1Cache(size = '64kB')) - switch_cpus[i].connectMemPorts(testsys.membus) - else: + if not options.caches: # O3 CPU must have a cache to work. switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) switch_cpus_1[i].connectMemPorts(testsys.membus) - root.switch_cpus = switch_cpus - root.switch_cpus_1 = switch_cpus_1 + testsys.switch_cpus = switch_cpus + testsys.switch_cpus_1 = switch_cpus_1 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] @@ -219,5 +211,5 @@ def run(options, root, testsys, cpu_class): if exit_cause == '': exit_cause = exit_event.getCause() - print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause + print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause) |