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author | Ronald Dreslinski <rdreslin@umich.edu> | 2012-01-26 14:53:48 -0500 |
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committer | Ronald Dreslinski <rdreslin@umich.edu> | 2012-01-26 14:53:48 -0500 |
commit | fc7cf40de672fdae5272cb7b69123a44ae274ed6 (patch) | |
tree | c65154f177c16eca830d6b474e41032ef5279069 /configs/common/Simulation.py | |
parent | 53c130bf2fdd4036b0988431c8cc32cfad06798e (diff) | |
download | gem5-fc7cf40de672fdae5272cb7b69123a44ae274ed6.tar.xz |
configs: A more realistic configuration of an ARM-like processor
Diffstat (limited to 'configs/common/Simulation.py')
-rw-r--r-- | configs/common/Simulation.py | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index 07cc323f9..193f8d487 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -34,6 +34,7 @@ import m5 from m5.defines import buildEnv from m5.objects import * from m5.util import * +from O3_ARM_v7a import * addToPath('../common') @@ -42,11 +43,14 @@ def setCPUClass(options): atomic = False if options.cpu_type == "timing": class TmpClass(TimingSimpleCPU): pass - elif options.cpu_type == "detailed": + elif options.cpu_type == "detailed" or options.cpu_type == "arm_detailed": if not options.caches and not options.ruby: print "O3 CPU must be used with caches" sys.exit(1) - class TmpClass(DerivO3CPU): pass + if options.cpu_type == "arm_detailed": + class TmpClass(O3_ARM_v7a_3): pass + else: + class TmpClass(DerivO3CPU): pass elif options.cpu_type == "inorder": if not options.caches: print "InOrder CPU must be used with caches" |