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authorLisa Hsu <hsul@eecs.umich.edu>2006-11-01 11:49:39 -0500
committerLisa Hsu <hsul@eecs.umich.edu>2006-11-01 11:49:39 -0500
commit7665be4f7066dcc65cacc010ca740a01d57e08d5 (patch)
treedc512766c3f0aed9cc497114b9f7448e815e4161 /configs/common/Simulation.py
parent9ef8bf74c7ab3d34889e804cb4b1e365da090d0b (diff)
downloadgem5-7665be4f7066dcc65cacc010ca740a01d57e08d5.tar.xz
make it so that you can do a standard switch without the caches option. this will have only the o3 cpu have a cache, rather than timing (warmup) + o3 have cache.
--HG-- extra : convert_revision : d733de7ebb362bbd7376a0235ee7f117df2d6d37
Diffstat (limited to 'configs/common/Simulation.py')
-rw-r--r--configs/common/Simulation.py7
1 files changed, 7 insertions, 0 deletions
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index a2b1d84d2..a10d588fa 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -64,9 +64,16 @@ def run(options, root, testsys):
switch_cpus_1[i].workload = testsys.cpu[i].workload
switch_cpus[i].clock = testsys.cpu[0].clock
switch_cpus_1[i].clock = testsys.cpu[0].clock
+
+ ## add caches to the warmup timing CPU (which will be
+ ## xferred to O3 when you switch again)
if options.caches:
switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
+ else: # O3 CPU must have a cache to work.
+ switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
+ L1Cache(size = '64kB'))
+ switch_cpus_1[i].connectMemPorts(testsys.membus)
switch_cpus[i].connectMemPorts(testsys.membus)