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| author | Korey Sewell <ksewell@umich.edu> | 2009-02-10 15:49:29 -0800 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2009-02-10 15:49:29 -0800 |
| commit | cf4a00ca410226d3fd1b4db816938b7ddf78a333 (patch) | |
| tree | f30f6ae1bbdaa1f01faceae5dd85ddf5efcea024 /configs/common/Simulation.py | |
| parent | 973d8b8b13b8e4ea178cafa95aaf6538699b8b15 (diff) | |
| download | gem5-cf4a00ca410226d3fd1b4db816938b7ddf78a333.tar.xz | |
Configs: Add support for the InOrder CPU model
Diffstat (limited to 'configs/common/Simulation.py')
| -rw-r--r-- | configs/common/Simulation.py | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index 3e4b8ec93..a771710fa 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -43,6 +43,11 @@ def setCPUClass(options): print "O3 CPU must be used with caches" sys.exit(1) class TmpClass(DerivO3CPU): pass + elif options.inorder: + if not options.caches: + print "InOrder CPU must be used with caches" + sys.exit(1) + class TmpClass(InOrderCPU): pass else: class TmpClass(AtomicSimpleCPU): pass atomic = True |