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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-01-23 11:33:52 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-01-23 11:33:52 -0600 |
| commit | 24c23009980a11dfba147fb4ed93329f4dcf4c0d (patch) | |
| tree | bba1acec6c459a1486b20726cd8375598073a712 /configs/common/Simulation.py | |
| parent | 63563c9df2eca46231768a448e981e8bb7856655 (diff) | |
| download | gem5-24c23009980a11dfba147fb4ed93329f4dcf4c0d.tar.xz | |
Config: Enable using O3 CPU and Ruby in SE mode
Diffstat (limited to 'configs/common/Simulation.py')
| -rw-r--r-- | configs/common/Simulation.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index 434fe8369..07cc323f9 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -43,7 +43,7 @@ def setCPUClass(options): if options.cpu_type == "timing": class TmpClass(TimingSimpleCPU): pass elif options.cpu_type == "detailed": - if not options.caches: + if not options.caches and not options.ruby: print "O3 CPU must be used with caches" sys.exit(1) class TmpClass(DerivO3CPU): pass |