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authorAndreas Sandberg <Andreas.Sandberg@ARM.com>2013-02-15 17:40:08 -0500
committerAndreas Sandberg <Andreas.Sandberg@ARM.com>2013-02-15 17:40:08 -0500
commit7cd1fd4324bc1f465a9f96a447d240ab697febd2 (patch)
tree5a18cd552a6258b732afd7c09f143130df25f157 /configs/common/Simulation.py
parentdb5c478e707ba5c7ffe8713ece5534924208500a (diff)
downloadgem5-7cd1fd4324bc1f465a9f96a447d240ab697febd2.tar.xz
cpu: Add CPU metadata om the Python classes
The configuration scripts currently hard-code the requirements of each CPU. This is clearly not optimal as it makes writing new configuration scripts painful and adding new CPU models requires existing scripts to be updated. This patch adds the following class methods to the base CPU and all relevant CPUs: * memory_mode -- Return a string describing the current memory mode (invalid/atomic/timing). * require_caches -- Does the CPU model require caches? * support_take_over -- Does the CPU support CPU handover?
Diffstat (limited to 'configs/common/Simulation.py')
-rw-r--r--configs/common/Simulation.py53
1 files changed, 25 insertions, 28 deletions
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index c8efd9619..70b21980e 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2006-2008 The Regents of The University of Michigan
# Copyright (c) 2010 Advanced Micro Devices, Inc.
# All rights reserved.
@@ -64,14 +76,11 @@ def setCPUClass(options):
depending on the options provided.
"""
- if options.cpu_type == "detailed" or \
- options.cpu_type == "arm_detailed" or \
- options.cpu_type == "inorder" :
- if not options.caches and not options.ruby:
- fatal("O3/Inorder CPU must be used with caches")
-
TmpClass, test_mem_mode = getCPUClass(options.cpu_type)
CPUClass = None
+ if TmpClass.require_caches() and \
+ not options.caches and not options.ruby:
+ fatal("%s must be used with caches" % options.cpu_type)
if options.checkpoint_restore != None:
if options.restore_with_cpu != options.cpu_type:
@@ -317,29 +326,17 @@ def run(options, root, testsys, cpu_class):
switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
if options.repeat_switch:
- if options.cpu_type == "arm_detailed":
- if not options.caches:
- print "O3 CPU must be used with caches"
- sys.exit(1)
-
- repeat_switch_cpus = [O3_ARM_v7a_3(switched_out=True, \
- cpu_id=(i)) for i in xrange(np)]
- elif options.cpu_type == "detailed":
- if not options.caches:
- print "O3 CPU must be used with caches"
- sys.exit(1)
-
- repeat_switch_cpus = [DerivO3CPU(switched_out=True, \
- cpu_id=(i)) for i in xrange(np)]
- elif options.cpu_type == "inorder":
- print "inorder CPU switching not supported"
+ switch_class = getCPUClass(options.cpu_type)[0]
+ if switch_class.require_caches() and \
+ not options.caches:
+ print "%s: Must be used with caches" % str(switch_class)
sys.exit(1)
- elif options.cpu_type == "timing":
- repeat_switch_cpus = [TimingSimpleCPU(switched_out=True, \
- cpu_id=(i)) for i in xrange(np)]
- else:
- repeat_switch_cpus = [AtomicSimpleCPU(switched_out=True, \
- cpu_id=(i)) for i in xrange(np)]
+ if not switch_class.support_take_over():
+ print "%s: CPU switching not supported" % str(switch_class)
+ sys.exit(1)
+
+ repeat_switch_cpus = [switch_class(switched_out=True, \
+ cpu_id=(i)) for i in xrange(np)]
for i in xrange(np):
repeat_switch_cpus[i].system = testsys