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authorGabe Black <gblack@eecs.umich.edu>2012-01-07 02:16:37 -0800
committerGabe Black <gblack@eecs.umich.edu>2012-01-07 02:16:37 -0800
commit241cc0c8402f1b9f2ec20d1cc152d96930959b2a (patch)
tree666717370cc9db4775ef46c10f7d8a92a34f40e2 /configs/common/Simulation.py
parentec936364b7238cddea7734ea79c6e04b52a683c6 (diff)
parent4b772782871f265cf7372c984ad750803396938c (diff)
downloadgem5-241cc0c8402f1b9f2ec20d1cc152d96930959b2a.tar.xz
Another merge with the main repository.
Diffstat (limited to 'configs/common/Simulation.py')
-rw-r--r--configs/common/Simulation.py6
1 files changed, 3 insertions, 3 deletions
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index 7abf478da..1897fa8cb 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -40,14 +40,14 @@ addToPath('../common')
def setCPUClass(options):
atomic = False
- if options.timing:
+ if options.cpu_type == "timing":
class TmpClass(TimingSimpleCPU): pass
- elif options.detailed:
+ elif options.cpu_type == "detailed":
if not options.caches:
print "O3 CPU must be used with caches"
sys.exit(1)
class TmpClass(DerivO3CPU): pass
- elif options.inorder:
+ elif options.cpu_type == "inorder":
if not options.caches:
print "InOrder CPU must be used with caches"
sys.exit(1)