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| author | Kevin Lim <ktlim@umich.edu> | 2006-11-09 15:06:00 -0500 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2006-11-09 15:06:00 -0500 |
| commit | 6591ebb09839586b6849cd28b7c888a2757ba676 (patch) | |
| tree | 0af7cab23e52bac2529049ec2abf8829479cdd9a /configs/common | |
| parent | f4aa4e43c41fa688abbee9dfa5b2a35a44b2dcf5 (diff) | |
| parent | 0ba2cc6571f80beb3600000649403cbff0b67d8b (diff) | |
| download | gem5-6591ebb09839586b6849cd28b7c888a2757ba676.tar.xz | |
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
--HG--
extra : convert_revision : dafe2d4a032b277c219ea13faf20567c20c1f2f4
Diffstat (limited to 'configs/common')
| -rw-r--r-- | configs/common/Simulation.py | 16 |
1 files changed, 4 insertions, 12 deletions
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index a67159a50..374ff3fc2 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -85,10 +85,6 @@ def run(options, root, testsys, cpu_class): if not m5.build_env['FULL_SYSTEM']: switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus[i].clock = testsys.cpu[0].clock - if options.caches: - switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), - L1Cache(size = '64kB')) - switch_cpus[i].connectMemPorts(testsys.membus) root.switch_cpus = switch_cpus switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] @@ -108,19 +104,15 @@ def run(options, root, testsys, cpu_class): switch_cpus[i].clock = testsys.cpu[0].clock switch_cpus_1[i].clock = testsys.cpu[0].clock - if options.caches: - switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), - L1Cache(size = '64kB')) - switch_cpus[i].connectMemPorts(testsys.membus) - else: + if not options.caches: # O3 CPU must have a cache to work. switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) switch_cpus_1[i].connectMemPorts(testsys.membus) - root.switch_cpus = switch_cpus - root.switch_cpus_1 = switch_cpus_1 + testsys.switch_cpus = switch_cpus + testsys.switch_cpus_1 = switch_cpus_1 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] @@ -219,5 +211,5 @@ def run(options, root, testsys, cpu_class): if exit_cause == '': exit_cause = exit_event.getCause() - print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause + print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause) |