summaryrefslogtreecommitdiff
path: root/configs/common
diff options
context:
space:
mode:
authorAndreas Hansson <andreas.hansson@arm.com>2012-10-25 04:32:44 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-10-25 04:32:44 -0400
commitd22796c03cba79307eac6a332cede20ca88f57cc (patch)
tree27672bcfa77f6fe77c6ddd8dc25c1033e1e706bd /configs/common
parent1fdc4e850e3e1fafb0b0c7cd7bd534c5cbe3013d (diff)
downloadgem5-d22796c03cba79307eac6a332cede20ca88f57cc.tar.xz
config: Use shared cache config for regressions
This patch uses the common L1, L2 and IOCache configuration for the regressions that all share the same cache parameters. There are a few regressions that use a slightly different configuration (memtest, o3-timing=mp, simple-atomic-mp and simple-timing-mp), and the latter are not changed in this patch. They will be updated in a future patch. The common cache configurations are changed to match the ones used in the regressions, and are slightly changed with respect to what they were. Hopefully this means we can converge on a common base configuration, used both in the normal user configurations and regressions. As only regressions that shared the same cache configuration are updated, no regressions are affected.
Diffstat (limited to 'configs/common')
-rw-r--r--configs/common/Caches.py36
1 files changed, 22 insertions, 14 deletions
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 0b5f9e182..867d0cb2e 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -40,22 +40,40 @@
from m5.objects import *
-class L1Cache(BaseCache):
+# Base implementations of L1, L2, IO and TLB-walker caches. There are
+# used in the regressions and also as base components in the
+# system-configuration scripts. The values are meant to serve as a
+# starting point, and specific parameters can be overridden in the
+# specific instantiations.
+
+class L1(BaseCache):
assoc = 2
- block_size = 64
hit_latency = 2
response_latency = 2
- mshrs = 10
+ block_size = 64
+ mshrs = 4
tgts_per_mshr = 20
is_top_level = True
-class L2Cache(BaseCache):
+class L2(BaseCache):
assoc = 8
block_size = 64
hit_latency = 20
response_latency = 20
+ mshrs = 92
+ tgts_per_mshr = 16
+ write_buffers = 8
+
+class IOCache(BaseCache):
+ assoc = 8
+ block_size = 64
+ hit_latency = 50
+ response_latency = 50
mshrs = 20
+ size = '1kB'
tgts_per_mshr = 12
+ forward_snoops = False
+ is_top_level = True
class PageTableWalkerCache(BaseCache):
assoc = 2
@@ -67,13 +85,3 @@ class PageTableWalkerCache(BaseCache):
tgts_per_mshr = 12
is_top_level = True
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- forward_snoops = False
- is_top_level = True