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| author | Kevin Lim <ktlim@umich.edu> | 2006-11-09 15:05:13 -0500 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2006-11-09 15:05:13 -0500 |
| commit | 0ba2cc6571f80beb3600000649403cbff0b67d8b (patch) | |
| tree | 0c7e677007e197fc2b6f47fdfdff816ff660c54e /configs/common | |
| parent | 21f43bfc4b01051e688a4eec4ce5aef12ad2c951 (diff) | |
| download | gem5-0ba2cc6571f80beb3600000649403cbff0b67d8b.tar.xz | |
Clean up config scripts to not have to worry about attaching a cache only to the TimingCPU. Now the Atomic CPU works with caches.
configs/common/Simulation.py:
Atomic CPU now works properly with caches, so we don't have to do extra parsing to hook up caches only to the timing CPU.
However the O3CPU must always use caches, so a check for that must still exist.
Also change the switch_cpus to be placed at the system level, now that Steve changed how the IntrController gets its CPU.
configs/example/fs.py:
configs/example/se.py:
Atomic CPU now handles caches.
--HG--
extra : convert_revision : 534ded558ef96cafd76b4b5c5317bd8f4d05076e
Diffstat (limited to 'configs/common')
| -rw-r--r-- | configs/common/Simulation.py | 16 |
1 files changed, 4 insertions, 12 deletions
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index d88373d54..f43fa9a6f 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -84,10 +84,6 @@ def run(options, root, testsys, cpu_class): if not m5.build_env['FULL_SYSTEM']: switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus[i].clock = testsys.cpu[0].clock - if options.caches: - switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), - L1Cache(size = '64kB')) - switch_cpus[i].connectMemPorts(testsys.membus) root.switch_cpus = switch_cpus switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] @@ -107,19 +103,15 @@ def run(options, root, testsys, cpu_class): switch_cpus[i].clock = testsys.cpu[0].clock switch_cpus_1[i].clock = testsys.cpu[0].clock - if options.caches: - switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), - L1Cache(size = '64kB')) - switch_cpus[i].connectMemPorts(testsys.membus) - else: + if not options.caches: # O3 CPU must have a cache to work. switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) switch_cpus_1[i].connectMemPorts(testsys.membus) - root.switch_cpus = switch_cpus - root.switch_cpus_1 = switch_cpus_1 + testsys.switch_cpus = switch_cpus + testsys.switch_cpus_1 = switch_cpus_1 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] @@ -222,5 +214,5 @@ def run(options, root, testsys, cpu_class): if exit_cause == '': exit_cause = exit_event.getCause() - print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause + print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause) |