Merge zizzer:/bk/newmem

into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

configs/example/fs.py:
configs/example/se.py:
    hand merge

--HG--
extra : convert_revision : 13d248add87ac373d2653bb42adf4ac065f75ce3

3 files changed, 271 insertions, 0 deletions

diff --git a/configs/common/Caches.py b/configs/common/Caches.py
new file mode 100644
index 000000000..d86fba246
--- /dev/null
+++ b/configs/common/Caches.py
@@ -0,0 +1,39 @@
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Lisa Hsu
+
+import m5
+from m5.objects import *
+
+class L1Cache(BaseCache):
+    assoc = 2
+    block_size = 64
+    latency = 1
+    mshrs = 10
+    tgts_per_mshr = 5
+    protocol = CoherenceProtocol(protocol='moesi')
+
diff --git a/configs/common/Options.py b/configs/common/Options.py
new file mode 100644
index 000000000..d9c1cc64e
--- /dev/null
+++ b/configs/common/Options.py
@@ -0,0 +1,57 @@
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Lisa Hsu
+
+# system options
+parser.add_option("-d", "--detailed", action="store_true")
+parser.add_option("-t", "--timing", action="store_true")
+parser.add_option("-n", "--num_cpus", type="int", default=1)
+parser.add_option("--caches", action="store_true")
+
+# Run duration options
+parser.add_option("-m", "--maxtick", type="int")
+parser.add_option("--maxtime", type="float")
+
+# Checkpointing options
+###Note that performing checkpointing via python script files will override
+###checkpoint instructions built into binaries.
+parser.add_option("--take_checkpoints", action="store", type="string",
+                  help="<M,N> will take checkpoint at cycle M and every N cycles \
+                  thereafter")
+parser.add_option("--max_checkpoints", action="store", type="int",
+                  help="the maximum number of checkpoints to drop",
+                  default=5)
+parser.add_option("--checkpoint_dir", action="store", type="string",
+                  help="Place all checkpoints in this absolute directory")
+parser.add_option("-r", "--checkpoint_restore", action="store", type="int",
+                  help="restore from checkpoint <N>")
+
+# CPU Switching - default switch model goes from a checkpoint
+# to a timing simple CPU with caches to warm up, then to detailed CPU for
+# data measurement
+parser.add_option("-s", "--standard_switch", action="store_true",
+                  help="switch from one cpu mode to another")
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
new file mode 100644
index 000000000..b927315ba
--- /dev/null
+++ b/configs/common/Simulation.py
@@ -0,0 +1,175 @@
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Lisa Hsu
+
+from os import getcwd
+import m5
+from m5.objects import *
+m5.AddToPath('../common')
+from Caches import *
+
+def run(options, root, testsys):
+    if options.maxtick:
+        maxtick = options.maxtick
+    elif options.maxtime:
+        simtime = int(options.maxtime * root.clock.value)
+        print "simulating for: ", simtime
+        maxtick = simtime
+    else:
+        maxtick = -1
+
+    if options.checkpoint_dir:
+        cptdir = options.checkpoint_dir
+    else:
+        cptdir = getcwd()
+
+    np = options.num_cpus
+    max_checkpoints = options.max_checkpoints
+
+    if options.standard_switch:
+        switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
+                       for i in xrange(np)]
+        switch_cpus1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
+                        for i in xrange(np)]
+        for i in xrange(np):
+            switch_cpus[i].system =  testsys
+            switch_cpus1[i].system =  testsys
+            if not m5.build_env['FULL_SYSTEM']:
+                switch_cpus[i].workload = testsys.cpu[i].workload
+                switch_cpus1[i].workload = testsys.cpu[i].workload
+            switch_cpus[i].clock = testsys.cpu[0].clock
+            switch_cpus1[i].clock = testsys.cpu[0].clock
+            if options.caches:
+                switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
+                                                       L1Cache(size = '64kB'))
+
+            switch_cpus[i].mem = testsys.physmem
+            switch_cpus1[i].mem = testsys.physmem
+            switch_cpus[i].connectMemPorts(testsys.membus)
+            root.switch_cpus = switch_cpus
+            root.switch_cpus1 = switch_cpus1
+            switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
+            switch_cpu_list1 = [(switch_cpus[i], switch_cpus1[i]) for i in xrange(np)]
+
+    m5.instantiate(root)
+
+    if options.checkpoint_restore:
+        from os.path import isdir
+        from os import listdir
+        import re
+
+        if not isdir(cptdir):
+            m5.panic("checkpoint dir %s does not exist!" % cptdir)
+
+        dirs = listdir(cptdir)
+        expr = re.compile('cpt.([0-9]*)')
+        cpts = []
+        for dir in dirs:
+            match = expr.match(dir)
+            if match:
+                cpts.append(match.group(1))
+
+        cpts.sort(lambda a,b: cmp(long(a), long(b)))
+
+        cpt_num = options.checkpoint_restore
+
+        if cpt_num > len(cpts):
+            m5.panic('Checkpoint %d not found' % cpt_num)
+
+        m5.restoreCheckpoint(root,
+                             "/".join([cptdir, "cpt.%s" % cpts[cpt_num - 1]]))
+
+    if options.standard_switch:
+        exit_event = m5.simulate(10000)
+
+        ## when you change to Timing (or Atomic), you halt the system given
+        ## as argument.  When you are finished with the system changes
+        ## (including switchCpus), you must resume the system manually.
+        ## You DON'T need to resume after just switching CPUs if you haven't
+        ## changed anything on the system level.
+
+        m5.changeToTiming(testsys)
+        m5.switchCpus(switch_cpu_list)
+        m5.resume(testsys)
+
+        exit_event = m5.simulate(3000000)
+        m5.switchCpus(switch_cpu_list1)
+
+    num_checkpoints = 0
+    exit_cause = ''
+
+    if options.take_checkpoints:
+        [when, period] = options.take_checkpoints.split(",", 1)
+        when = int(when)
+        period = int(period)
+
+        print "when is ", when, " period is ", period
+        exit_event = m5.simulate(when)
+        while exit_event.getCause() == "checkpoint":
+            exit_event = m5.simulate(when - m5.curTick())
+
+        if exit_event.getCause() == "simulate() limit reached":
+            m5.checkpoint(root, cptdir + "cpt.%d")
+            num_checkpoints += 1
+
+        sim_ticks = when
+        exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
+        while num_checkpoints < max_checkpoints:
+            if (sim_ticks + period) > maxtick and maxtick != -1:
+                exit_event = m5.simulate(maxtick - sim_ticks)
+                exit_cause = exit_event.getCause()
+                break
+            else:
+                exit_event = m5.simulate(period)
+                sim_ticks += period
+                while exit_event.getCause() == "checkpoint":
+                    exit_event = m5.simulate(sim_ticks - m5.curTick())
+                if exit_event.getCause() == "simulate() limit reached":
+                    m5.checkpoint(root, cptdir + "cpt.%d")
+                    num_checkpoints += 1
+
+    else: #no checkpoints being taken via this script
+        exit_event = m5.simulate(maxtick)
+
+        while exit_event.getCause() == "checkpoint":
+            m5.checkpoint(root, cptdir + "cpt.%d")
+            num_checkpoints += 1
+            if num_checkpoints == max_checkpoints:
+                exit_cause =  "maximum %d checkpoints dropped" % max_checkpoints
+                break
+
+            if maxtick == -1:
+                exit_event = m5.simulate(maxtick)
+            else:
+                exit_event = m5.simulate(maxtick - m5.curTick())
+
+            exit_cause = exit_event.getCause()
+
+    if exit_cause == '':
+        exit_cause = exit_event.getCause()
+    print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause
+