diff options
| author | Sophiane Senni <sophiane.senni@gmail.com> | 2016-11-30 17:10:27 -0500 |
|---|---|---|
| committer | Sophiane Senni <sophiane.senni@gmail.com> | 2016-11-30 17:10:27 -0500 |
| commit | ce2722cdd97a31f85d36f6c32637b230e3c25c73 (patch) | |
| tree | 72993532267d3f1f99e8519be837dd7c523a722f /configs/common | |
| parent | 047caf24ba9a640247b63584c2291e760f1f4d54 (diff) | |
| download | gem5-ce2722cdd97a31f85d36f6c32637b230e3c25c73.tar.xz | |
mem: Split the hit_latency into tag_latency and data_latency
If the cache access mode is parallel, i.e. "sequential_access" parameter
is set to "False", tags and data are accessed in parallel. Therefore,
the hit_latency is the maximum latency between tag_latency and
data_latency. On the other hand, if the cache access mode is
sequential, i.e. "sequential_access" parameter is set to "True",
tags and data are accessed sequentially. Therefore, the hit_latency
is the sum of tag_latency plus data_latency.
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'configs/common')
| -rw-r--r-- | configs/common/Caches.py | 12 | ||||
| -rw-r--r-- | configs/common/O3_ARM_v7a.py | 12 |
2 files changed, 16 insertions, 8 deletions
diff --git a/configs/common/Caches.py b/configs/common/Caches.py index af1dee626..acaa0024e 100644 --- a/configs/common/Caches.py +++ b/configs/common/Caches.py @@ -48,7 +48,8 @@ from m5.objects import * class L1Cache(Cache): assoc = 2 - hit_latency = 2 + tag_latency = 2 + data_latency = 2 response_latency = 2 mshrs = 4 tgts_per_mshr = 20 @@ -63,7 +64,8 @@ class L1_DCache(L1Cache): class L2Cache(Cache): assoc = 8 - hit_latency = 20 + tag_latency = 20 + data_latency = 20 response_latency = 20 mshrs = 20 tgts_per_mshr = 12 @@ -71,7 +73,8 @@ class L2Cache(Cache): class IOCache(Cache): assoc = 8 - hit_latency = 50 + tag_latency = 50 + data_latency = 50 response_latency = 50 mshrs = 20 size = '1kB' @@ -79,7 +82,8 @@ class IOCache(Cache): class PageTableWalkerCache(Cache): assoc = 2 - hit_latency = 2 + tag_latency = 2 + data_latency = 2 response_latency = 2 mshrs = 10 size = '1kB' diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py index 3def4a3f2..f5c2c711a 100644 --- a/configs/common/O3_ARM_v7a.py +++ b/configs/common/O3_ARM_v7a.py @@ -147,7 +147,8 @@ class O3_ARM_v7a_3(DerivO3CPU): # Instruction Cache class O3_ARM_v7a_ICache(Cache): - hit_latency = 1 + tag_latency = 1 + data_latency = 1 response_latency = 1 mshrs = 2 tgts_per_mshr = 8 @@ -159,7 +160,8 @@ class O3_ARM_v7a_ICache(Cache): # Data Cache class O3_ARM_v7a_DCache(Cache): - hit_latency = 2 + tag_latency = 2 + data_latency = 2 response_latency = 2 mshrs = 6 tgts_per_mshr = 8 @@ -172,7 +174,8 @@ class O3_ARM_v7a_DCache(Cache): # TLB Cache # Use a cache as a L2 TLB class O3_ARM_v7aWalkCache(Cache): - hit_latency = 4 + tag_latency = 4 + data_latency = 4 response_latency = 4 mshrs = 6 tgts_per_mshr = 8 @@ -185,7 +188,8 @@ class O3_ARM_v7aWalkCache(Cache): # L2 Cache class O3_ARM_v7aL2(Cache): - hit_latency = 12 + tag_latency = 12 + data_latency = 12 response_latency = 12 mshrs = 16 tgts_per_mshr = 8 |