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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-04-21 08:17:36 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-04-21 08:17:36 -0700 |
| commit | 97b6947eb767ba1a7750525123c0c517223cee43 (patch) | |
| tree | c8fd753d9ad79d521c1ab3b47bad75c19e26f5d1 /configs/common | |
| parent | eb3b6935d3a4afc65be3ef16584be78572d4a39c (diff) | |
| download | gem5-97b6947eb767ba1a7750525123c0c517223cee43.tar.xz | |
Minor tweaks for future Ruby compatibility.
Diffstat (limited to 'configs/common')
| -rw-r--r-- | configs/common/Simulation.py | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index a771710fa..0004e4fe6 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -31,7 +31,6 @@ from os.path import join as joinpath import m5 from m5.objects import * m5.AddToPath('../common') -from Caches import L1Cache def setCPUClass(options): @@ -151,9 +150,8 @@ def run(options, root, testsys, cpu_class): if not options.caches: # O3 CPU must have a cache to work. - switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), - L1Cache(size = '64kB')) - switch_cpus_1[i].connectMemPorts(testsys.membus) + print "O3 CPU must be used with caches" + sys.exit(1) testsys.switch_cpus = switch_cpus testsys.switch_cpus_1 = switch_cpus_1 |