More restructuring of regression tests.

Moving work back to zizzer...

configs/common/FSConfig.py:
configs/test/fs.py:
    Move CPU connections out of makeLinuxAlphaSystem()
src/python/m5/objects/BaseCPU.py:
    Create default TLBs in full system.
    Move utility cache functions here.
src/python/m5/objects/O3CPU.py:
    Add _mem_ports
tests/run.py:
    Add binpath()
    Change maxtick default to 'forever'
tests/simple-atomic.py:
    Use connectmemPorts()
tests/simple-timing.py:
    Fix up.

--HG--
rename : tests/quick/eio1/ref/alpha/eio/detailed/config.ini => tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini
rename : tests/quick/eio1/ref/alpha/eio/detailed/config.out => tests/quick/20.eio-short/ref/alpha/eio/detailed/config.out
rename : tests/quick/eio1/ref/alpha/eio/detailed/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt
rename : tests/quick/eio1/ref/alpha/eio/detailed/stderr => tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr
rename : tests/quick/eio1/ref/alpha/eio/detailed/stdout => tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/config.ini => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/config.out => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/config.ini => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/config.out => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
rename : tests/quick/eio1/test.py => tests/quick/20.eio-short/test.py
rename : configs/test/hello => tests/test-progs/hello/bin/alpha/linux/hello
rename : configs/test/hello_mips => tests/test-progs/hello/bin/mips/linux/hello_mips
rename : configs/test/sparc_tests/hello_sparc => tests/test-progs/hello/bin/sparc/bin
extra : convert_revision : 1f891392ecc11ffcc3b3182fa673c401c0efc8a5

1 files changed, 1 insertions, 8 deletions

diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index c6ad8ce48..7d62297a9 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -31,7 +31,6 @@ from m5 import makeList
 from m5.objects import *
 from Benchmarks import *
 from FullO3Config import *
-from Util import *
 
 class CowIdeDisk(IdeDisk):
     image = CowDiskImage(child=RawDiskImage(read_only=True),
@@ -47,7 +46,7 @@ class BaseTsunami(Tsunami):
     ide = IdeController(disks=[Parent.disk0, Parent.disk2],
                         pci_func=0, pci_dev=0, pci_bus=0)
 
-def makeLinuxAlphaSystem(cpu, mem_mode, mdesc, icache=None, dcache=None, l2cache=None):
+def makeLinuxAlphaSystem(mem_mode, mdesc):
     self = LinuxAlphaSystem()
     self.readfile = mdesc.script()
     self.iobus = Bus(bus_id=0)
@@ -72,13 +71,7 @@ def makeLinuxAlphaSystem(cpu, mem_mode, mdesc, icache=None, dcache=None, l2cache
     self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
                                                read_only = True))
     self.intrctrl = IntrControl()
-    self.cpu = cpu
     self.mem_mode = mem_mode
-    connectCpu(self.cpu, self.membus, icache, dcache, l2cache)
-    for each_cpu in makeList(self.cpu):
-        each_cpu.itb = AlphaITB()
-        each_cpu.dtb = AlphaDTB()
-    self.cpu.clock = '2GHz'
     self.sim_console = SimConsole(listener=ConsoleListener(port=3456))
     self.kernel = binary('vmlinux')
     self.pal = binary('ts_osfpal')