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authorAndreas Hansson <andreas.hansson@arm.com>2014-03-23 11:12:12 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2014-03-23 11:12:12 -0400
commit7c18691db1bc450b04142502e5c324ad612318ab (patch)
tree10083265e3854227c8946f861db127c7d783f2e0 /configs/common
parent3dd1587afc48e8d2b870253de689bbe7262fcbe6 (diff)
downloadgem5-7c18691db1bc450b04142502e5c324ad612318ab.tar.xz
mem: Rename SimpleDRAM to a more suitable DRAMCtrl
This patch renames the not-so-simple SimpleDRAM to a more suitable DRAMCtrl. The name change is intended to ensure that we do not send the wrong message (although the "simple" in SimpleDRAM was originally intended as in cleverly simple, or elegant). As the DRAM controller modelling work is being presented at ISPASS'14 our hope is that a broader audience will use the model in the future. --HG-- rename : src/mem/SimpleDRAM.py => src/mem/DRAMCtrl.py rename : src/mem/simple_dram.cc => src/mem/dram_ctrl.cc rename : src/mem/simple_dram.hh => src/mem/dram_ctrl.hh
Diffstat (limited to 'configs/common')
-rw-r--r--configs/common/MemConfig.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index e5e701716..e954407bc 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -160,7 +160,7 @@ def config_mem(options, system):
ctrl = cls()
# Only do this for DRAMs
- if issubclass(cls, m5.objects.SimpleDRAM):
+ if issubclass(cls, m5.objects.DRAMCtrl):
# Inform each controller how many channels to account
# for
ctrl.channels = nbr_mem_ctrls