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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 02:39:19 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 02:39:19 -0700 |
| commit | 06d25dcd26bda01ec1377d7c9ecdc3d4d05c49ce (patch) | |
| tree | f82e5bac209edbf958373830a285d6ad73b611ff /configs/common | |
| parent | d10195b1a4d331f2db99161bd6ed546e6d3cd31d (diff) | |
| download | gem5-06d25dcd26bda01ec1377d7c9ecdc3d4d05c49ce.tar.xz | |
X86: Automatically make the IO APIC in an N CPU system have id N+1.
Diffstat (limited to 'configs/common')
| -rw-r--r-- | configs/common/FSConfig.py | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index 3737a2765..5b5b9fc32 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -223,7 +223,7 @@ def makeX86System(mem_mode, mdesc = None, self = None): trigger = 'ConformTrigger', source_bus_id = 1, source_bus_irq = 0 + (4 << 2), - dest_io_apic_id = 1, + dest_io_apic_id = io_apic.id, dest_io_apic_intin = 16) assign_8259_0_to_apic = X86IntelMPIOIntAssignment( interrupt_type = 'ExtInt', @@ -231,7 +231,7 @@ def makeX86System(mem_mode, mdesc = None, self = None): trigger = 'ConformTrigger', source_bus_id = 0, source_bus_irq = 0, - dest_io_apic_id = 1, + dest_io_apic_id = io_apic.id, dest_io_apic_intin = 0) self.intel_mp_table.add_entry(assign_8259_0_to_apic) assign_0_to_apic = X86IntelMPIOIntAssignment( @@ -240,7 +240,7 @@ def makeX86System(mem_mode, mdesc = None, self = None): trigger = 'ConformTrigger', source_bus_id = 0, source_bus_irq = 0, - dest_io_apic_id = 1, + dest_io_apic_id = io_apic.id, dest_io_apic_intin = 2) self.intel_mp_table.add_entry(assign_0_to_apic) assign_8259_1_to_apic = X86IntelMPIOIntAssignment( @@ -249,7 +249,7 @@ def makeX86System(mem_mode, mdesc = None, self = None): trigger = 'ConformTrigger', source_bus_id = 0, source_bus_irq = 1, - dest_io_apic_id = 1, + dest_io_apic_id = io_apic.id, dest_io_apic_intin = 0) self.intel_mp_table.add_entry(assign_8259_1_to_apic) assign_1_to_apic = X86IntelMPIOIntAssignment( @@ -258,7 +258,7 @@ def makeX86System(mem_mode, mdesc = None, self = None): trigger = 'ConformTrigger', source_bus_id = 0, source_bus_irq = 1, - dest_io_apic_id = 1, + dest_io_apic_id = io_apic.id, dest_io_apic_intin = 1) self.intel_mp_table.add_entry(assign_1_to_apic) assign_8259_4_to_apic = X86IntelMPIOIntAssignment( @@ -267,7 +267,7 @@ def makeX86System(mem_mode, mdesc = None, self = None): trigger = 'ConformTrigger', source_bus_id = 0, source_bus_irq = 4, - dest_io_apic_id = 1, + dest_io_apic_id = io_apic.id, dest_io_apic_intin = 0) self.intel_mp_table.add_entry(assign_8259_4_to_apic) assign_4_to_apic = X86IntelMPIOIntAssignment( @@ -276,7 +276,7 @@ def makeX86System(mem_mode, mdesc = None, self = None): trigger = 'ConformTrigger', source_bus_id = 0, source_bus_irq = 4, - dest_io_apic_id = 1, + dest_io_apic_id = io_apic.id, dest_io_apic_intin = 4) self.intel_mp_table.add_entry(assign_4_to_apic) assign_8259_12_to_apic = X86IntelMPIOIntAssignment( @@ -285,7 +285,7 @@ def makeX86System(mem_mode, mdesc = None, self = None): trigger = 'ConformTrigger', source_bus_id = 0, source_bus_irq = 12, - dest_io_apic_id = 1, + dest_io_apic_id = io_apic.id, dest_io_apic_intin = 0) self.intel_mp_table.add_entry(assign_8259_12_to_apic) assign_12_to_apic = X86IntelMPIOIntAssignment( @@ -294,7 +294,7 @@ def makeX86System(mem_mode, mdesc = None, self = None): trigger = 'ConformTrigger', source_bus_id = 0, source_bus_irq = 12, - dest_io_apic_id = 1, + dest_io_apic_id = io_apic.id, dest_io_apic_intin = 12) self.intel_mp_table.add_entry(assign_12_to_apic) assign_8259_14_to_apic = X86IntelMPIOIntAssignment( @@ -303,7 +303,7 @@ def makeX86System(mem_mode, mdesc = None, self = None): trigger = 'ConformTrigger', source_bus_id = 0, source_bus_irq = 14, - dest_io_apic_id = 1, + dest_io_apic_id = io_apic.id, dest_io_apic_intin = 0) self.intel_mp_table.add_entry(assign_8259_14_to_apic) assign_14_to_apic = X86IntelMPIOIntAssignment( @@ -312,7 +312,7 @@ def makeX86System(mem_mode, mdesc = None, self = None): trigger = 'ConformTrigger', source_bus_id = 0, source_bus_irq = 14, - dest_io_apic_id = 1, + dest_io_apic_id = io_apic.id, dest_io_apic_intin = 14) self.intel_mp_table.add_entry(assign_14_to_apic) |