mem: Allow read-only caches and check compliance

This patch adds a parameter to the BaseCache to enable a read-only
cache, for example for the instruction cache, or table-walker cache
(not for x86). A number of checks are put in place in the code to
ensure a read-only cache does not end up with dirty data.

A follow-on patch adds suitable read requests to allow a read-only
cache to explicitly ask for clean data.

3 files changed, 14 insertions, 1 deletions

diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 899090af5..d54df7490 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -64,7 +64,7 @@ def config_cache(options, system):
             O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2
     else:
         dcache_class, icache_class, l2_cache_class = \
-            L1Cache, L1Cache, L2Cache
+            L1_DCache, L1_ICache, L2Cache
 
     # Set the cache line size of the system
     system.cache_line_size = options.cacheline_size
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 6687a967c..2bdffc6c7 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -54,6 +54,12 @@ class L1Cache(BaseCache):
     tgts_per_mshr = 20
     is_top_level = True
 
+class L1_ICache(L1Cache):
+    is_read_only = True
+
+class L1_DCache(L1Cache):
+    pass
+
 class L2Cache(BaseCache):
     assoc = 8
     hit_latency = 20
@@ -81,3 +87,8 @@ class PageTableWalkerCache(BaseCache):
     tgts_per_mshr = 12
     forward_snoops = False
     is_top_level = True
+    # the x86 table walker actually writes to the table-walker cache
+    if buildEnv['TARGET_ISA'] == 'x86':
+        is_read_only = False
+    else:
+        is_read_only = True
diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py
index c291525ea..b4b66df9c 100644
--- a/configs/common/O3_ARM_v7a.py
+++ b/configs/common/O3_ARM_v7a.py
@@ -151,6 +151,7 @@ class O3_ARM_v7a_ICache(BaseCache):
     assoc = 2
     is_top_level = True
     forward_snoops = False
+    is_read_only = True
 
 # Data Cache
 class O3_ARM_v7a_DCache(BaseCache):
@@ -175,6 +176,7 @@ class O3_ARM_v7aWalkCache(BaseCache):
     write_buffers = 16
     is_top_level = True
     forward_snoops = False
+    is_read_only = True
 
 # L2 Cache
 class O3_ARM_v7aL2(BaseCache):