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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-08-21 07:03:23 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-08-21 07:03:23 -0400 |
| commit | ddfa96cf455ba4a287930942514cdf0f7f2afa77 (patch) | |
| tree | 89eddf6ab0ec6f4660629b45b1b7cff7df6ca82c /configs/common | |
| parent | d71a0d790d8d1113480c5a57d7bfbb9b7d0d0037 (diff) | |
| download | gem5-ddfa96cf455ba4a287930942514cdf0f7f2afa77.tar.xz | |
mem: Add explicit Cache subclass and make BaseCache abstract
Open up for other subclasses to BaseCache and transition to using the
explicit Cache subclass.
--HG--
rename : src/mem/cache/BaseCache.py => src/mem/cache/Cache.py
Diffstat (limited to 'configs/common')
| -rw-r--r-- | configs/common/Caches.py | 8 | ||||
| -rw-r--r-- | configs/common/O3_ARM_v7a.py | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/configs/common/Caches.py b/configs/common/Caches.py index cfb873b5e..0a3c56297 100644 --- a/configs/common/Caches.py +++ b/configs/common/Caches.py @@ -46,7 +46,7 @@ from m5.objects import * # starting point, and specific parameters can be overridden in the # specific instantiations. -class L1Cache(BaseCache): +class L1Cache(Cache): assoc = 2 hit_latency = 2 response_latency = 2 @@ -59,7 +59,7 @@ class L1_ICache(L1Cache): class L1_DCache(L1Cache): pass -class L2Cache(BaseCache): +class L2Cache(Cache): assoc = 8 hit_latency = 20 response_latency = 20 @@ -67,7 +67,7 @@ class L2Cache(BaseCache): tgts_per_mshr = 12 write_buffers = 8 -class IOCache(BaseCache): +class IOCache(Cache): assoc = 8 hit_latency = 50 response_latency = 50 @@ -76,7 +76,7 @@ class IOCache(BaseCache): tgts_per_mshr = 12 forward_snoops = False -class PageTableWalkerCache(BaseCache): +class PageTableWalkerCache(Cache): assoc = 2 hit_latency = 2 response_latency = 2 diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py index dbfdf6c41..9f250f57d 100644 --- a/configs/common/O3_ARM_v7a.py +++ b/configs/common/O3_ARM_v7a.py @@ -142,7 +142,7 @@ class O3_ARM_v7a_3(DerivO3CPU): branchPred = O3_ARM_v7a_BP() # Instruction Cache -class O3_ARM_v7a_ICache(BaseCache): +class O3_ARM_v7a_ICache(Cache): hit_latency = 1 response_latency = 1 mshrs = 2 @@ -153,7 +153,7 @@ class O3_ARM_v7a_ICache(BaseCache): is_read_only = True # Data Cache -class O3_ARM_v7a_DCache(BaseCache): +class O3_ARM_v7a_DCache(Cache): hit_latency = 2 response_latency = 2 mshrs = 6 @@ -164,7 +164,7 @@ class O3_ARM_v7a_DCache(BaseCache): # TLB Cache # Use a cache as a L2 TLB -class O3_ARM_v7aWalkCache(BaseCache): +class O3_ARM_v7aWalkCache(Cache): hit_latency = 4 response_latency = 4 mshrs = 6 @@ -176,7 +176,7 @@ class O3_ARM_v7aWalkCache(BaseCache): is_read_only = True # L2 Cache -class O3_ARM_v7aL2(BaseCache): +class O3_ARM_v7aL2(Cache): hit_latency = 12 response_latency = 12 mshrs = 16 |