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| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-08-20 11:46:12 -0700 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-08-20 11:46:12 -0700 |
| commit | 29c45ccd2322470d0d6cef0ae20600c8c68f97e9 (patch) | |
| tree | ec62739567ba7d442c8b65550507cdab6b7827dc /configs/common | |
| parent | 8e5c441a54b481085d6311f14af66e41b5766f91 (diff) | |
| download | gem5-29c45ccd2322470d0d6cef0ae20600c8c68f97e9.tar.xz | |
ruby: Reduced ruby latencies
The previous slower ruby latencies created a mismatch between the faster M5
cpu models and the much slower ruby memory system. Specifically smp
interrupts were much slower and infrequent, as well as cpus moving in and out
of spin locks. The result was many cpus were idle for large periods of time.
These changes fix the latency mismatch.
Diffstat (limited to 'configs/common')
| -rw-r--r-- | configs/common/Options.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/common/Options.py b/configs/common/Options.py index 4efbc541e..42e1585d7 100644 --- a/configs/common/Options.py +++ b/configs/common/Options.py @@ -34,7 +34,7 @@ parser.add_option("-n", "--num-cpus", type="int", default=1) parser.add_option("--caches", action="store_true") parser.add_option("--l2cache", action="store_true") parser.add_option("--fastmem", action="store_true") -parser.add_option("--clock", action="store", type="string", default='1GHz') +parser.add_option("--clock", action="store", type="string", default='2GHz') parser.add_option("--num-dirs", type="int", default=1) parser.add_option("--num-l2caches", type="int", default=1) parser.add_option("--num-l3caches", type="int", default=1) |