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| author | Steve Reinhardt <Steve.Reinhardt@amd.com> | 2008-07-16 11:10:33 -0700 |
|---|---|---|
| committer | Steve Reinhardt <Steve.Reinhardt@amd.com> | 2008-07-16 11:10:33 -0700 |
| commit | 6629d9b2bc58a885bfebce1517fd12483497b6e4 (patch) | |
| tree | 22e2bc30405ba483ac571951f49cc77d7e713477 /configs/common | |
| parent | 05d8c9acb8a5a985956998fc13551288496e5cdc (diff) | |
| download | gem5-6629d9b2bc58a885bfebce1517fd12483497b6e4.tar.xz | |
mem: use single BadAddr responder per system.
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond. Now there is just one on
the main memory bus. The default bus responder on all other buses
is now the downstream cache's cpu_side port. Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.
Diffstat (limited to 'configs/common')
| -rw-r--r-- | configs/common/Caches.py | 1 | ||||
| -rw-r--r-- | configs/common/FSConfig.py | 13 |
2 files changed, 10 insertions, 4 deletions
diff --git a/configs/common/Caches.py b/configs/common/Caches.py index f1ea957b5..1c3b089c7 100644 --- a/configs/common/Caches.py +++ b/configs/common/Caches.py @@ -50,3 +50,4 @@ class IOCache(BaseCache): mshrs = 20 size = '1kB' tgts_per_mshr = 12 + forward_snoops = False diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index 974003005..a9cd24ba3 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -38,6 +38,11 @@ class CowIdeDisk(IdeDisk): def childImage(self, ci): self.image.child.image_file = ci +class MemBus(Bus): + badaddr_responder = BadAddr() + default = Self.badaddr_responder.pio + + def makeLinuxAlphaSystem(mem_mode, mdesc = None): class BaseTsunami(Tsunami): ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) @@ -50,7 +55,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None): mdesc = SysConfig() self.readfile = mdesc.script() self.iobus = Bus(bus_id=0) - self.membus = Bus(bus_id=1) + self.membus = MemBus(bus_id=1) self.bridge = Bridge(delay='50ns', nack_delay='4ns') self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) self.bridge.side_a = self.iobus.port @@ -90,7 +95,7 @@ def makeSparcSystem(mem_mode, mdesc = None): mdesc = SysConfig() self.readfile = mdesc.script() self.iobus = Bus(bus_id=0) - self.membus = Bus(bus_id=1) + self.membus = MemBus(bus_id=1) self.bridge = Bridge(delay='50ns', nack_delay='4ns') self.t1000 = T1000() self.t1000.attachOnChipIO(self.membus) @@ -130,7 +135,7 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None): mdesc = SysConfig() self.readfile = mdesc.script() self.iobus = Bus(bus_id=0) - self.membus = Bus(bus_id=1) + self.membus = MemBus(bus_id=1) self.bridge = Bridge(delay='50ns', nack_delay='4ns') self.physmem = PhysicalMemory(range = AddrRange('1GB')) self.bridge.side_a = self.iobus.port @@ -170,7 +175,7 @@ def makeX86System(mem_mode, mdesc = None, self = None): self.readfile = mdesc.script() # Physical memory - self.membus = Bus(bus_id=1) + self.membus = MemBus(bus_id=1) self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) self.physmem.port = self.membus.port |