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authorNikos Nikoleris <nikos.nikoleris@arm.com>2018-02-05 11:38:32 +0000
committerNikos Nikoleris <nikos.nikoleris@arm.com>2018-03-02 16:16:17 +0000
commitd7de6dff7707ac48303231ee4a4f5790f9495304 (patch)
treea488c9488745b9fa273879d786b5be321ced60a9 /configs/dram
parent2a714355506200d281175e49f3a5c7886ce3df7d (diff)
downloadgem5-d7de6dff7707ac48303231ee4a4f5790f9495304.tar.xz
configs: Fix L3Cache instantiation in lat_mem_rd.py
This changeset updates the lat_mem_rd.py to configure the L3Cache using the split tag_latency, data_latency parameters. Change-Id: I8bc41d5f7664111bdda0972356d1a17762aa77e5 Reviewed-on: https://gem5-review.googlesource.com/8288 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Diffstat (limited to 'configs/dram')
-rw-r--r--configs/dram/lat_mem_rd.py4
1 files changed, 3 insertions, 1 deletions
diff --git a/configs/dram/lat_mem_rd.py b/configs/dram/lat_mem_rd.py
index ddc44e229..dc0cfcbb8 100644
--- a/configs/dram/lat_mem_rd.py
+++ b/configs/dram/lat_mem_rd.py
@@ -264,7 +264,9 @@ from common.Caches import *
# a starting point for an L3 cache
class L3Cache(Cache):
assoc = 16
- hit_latency = 40
+ tag_latency = 20
+ data_latency = 20
+ sequential_access = True
response_latency = 40
mshrs = 32
tgts_per_mshr = 12