diff options
| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2016-12-05 16:48:29 -0500 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2016-12-05 16:48:29 -0500 |
| commit | 0054f1ad53f00621df82d201b38c03f088786d27 (patch) | |
| tree | afa111820f0bd5582bb7b12629649c2a9d67e08a /configs/example/apu_se.py | |
| parent | 9916e4276cf7d5354e8e95c239698ee38a7f8674 (diff) | |
| download | gem5-0054f1ad53f00621df82d201b38c03f088786d27.tar.xz | |
mem: Respond to InvalidateReq when the block is (pending) dirty
Previously when an InvalidateReq snooped a cache with a dirty block or
a pending modified MSHR, it would invalidate the block or set the
postInv flag. The cache would not send an InvalidateResp. though,
causing memory order violations. This patches changes this behavior,
making the cache with the dirty block or pending modified MSHR the
ordering point.
Change-Id: Ib4c31012f4f6693ffb137cd77258b160fbc239ca
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Diffstat (limited to 'configs/example/apu_se.py')
0 files changed, 0 insertions, 0 deletions