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| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-03-17 11:10:55 +0000 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-04-03 16:37:55 +0000 |
| commit | 9a13acaa367769c38859342de9bc35aac59a6710 (patch) | |
| tree | 5d9b97eaed470df36e524fc4e44d171a3c228725 /configs/example/arm/devices.py | |
| parent | 3547af6e449c4bc0797c1c333bdce9c1c3ee2b66 (diff) | |
| download | gem5-9a13acaa367769c38859342de9bc35aac59a6710.tar.xz | |
config, arm: Add multi-core KVM support to bL config
Add support for KVM in the big.LITTLE(tm) example configuration. This
replaces the --atomic option with a --cpu-type option that can be used
to switch between atomic, kvm, and timing simulation.
When running in KVM mode, the simulation script automatically assigns
separate event queues (threads) to each of the simulated CPUs. All
simulated devices, including CPU child devices (e.g., interrupt
controllers and caches), are assigned to event queue 0.
Change-Id: Ic9a3f564db91f5a3d3cb754c5a02fdd5c17d5fdf
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2561
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Weiping Liao <weipingliao@google.com>
Diffstat (limited to 'configs/example/arm/devices.py')
| -rw-r--r-- | configs/example/arm/devices.py | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py index 7d3f383f3..f7375cd9a 100644 --- a/configs/example/arm/devices.py +++ b/configs/example/arm/devices.py @@ -1,4 +1,4 @@ -# Copyright (c) 2016 ARM Limited +# Copyright (c) 2016-2017 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -44,6 +44,8 @@ m5.util.addToPath('../../') from common.Caches import * from common import CpuConfig +have_kvm = "kvm" in CpuConfig.cpu_names() + class L1I(L1_ICache): tag_latency = 1 data_latency = 1 @@ -170,6 +172,14 @@ class AtomicCluster(CpuCluster): def addL1(self): pass +class KvmCluster(CpuCluster): + def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"): + cpu_config = [ CpuConfig.get("kvm"), None, None, None, None ] + super(KvmCluster, self).__init__(system, num_cpus, cpu_clock, + cpu_voltage, *cpu_config) + def addL1(self): + pass + class SimpleSystem(LinuxArmSystem): cache_line_size = 64 |